From: Jesse Barnes Date: Thu, 1 Nov 2007 22:27:55 +0000 (-0700) Subject: Merge branch 'master' into modesetting-101 X-Git-Tag: libdrm-2.4.3~16^2~366 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=629c8b0dbf975632473d848f60606baf309f2f3b;p=platform%2Fupstream%2Flibdrm.git Merge branch 'master' into modesetting-101 Conflicts: linux-core/Makefile.kernel linux-core/drm_stub.c linux-core/i915_drv.c shared-core/i915_dma.c shared-core/i915_drv.h Fixup suspend/resume conflicts (basically use what's in DRM master for now). Also fix up a few other conflicts that snuck in (i915_dma changes etc.). --- 629c8b0dbf975632473d848f60606baf309f2f3b diff --cc linux-core/Makefile.kernel index 0ed5471,bcbd78f..fd6f577 --- a/linux-core/Makefile.kernel +++ b/linux-core/Makefile.kernel @@@ -20,11 -19,10 +20,12 @@@ r128-objs := r128_drv.o r128_cce.o r1 mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o i810-objs := i810_drv.o i810_dma.o i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \ - i915_buffer.o i915_compat.o + i915_buffer.o intel_display.o intel_crt.o intel_lvds.o \ - intel_sdvo.o intel_modes.o intel_i2c.o i915_init.o intel_fb.o ++ intel_sdvo.o intel_modes.o intel_i2c.o i915_init.o intel_fb.o \ ++ i915_compat.o nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \ nouveau_object.o nouveau_irq.o nouveau_notifier.o nouveau_swmthd.o \ - nouveau_sgdma.o nouveau_dma.o \ + nouveau_sgdma.o nouveau_dma.o nouveau_buffer.o \ nv04_timer.o \ nv04_mc.o nv40_mc.o nv50_mc.o \ nv04_fb.o nv10_fb.o nv40_fb.o \ diff --cc linux-core/i915_drv.c index 27e95d6,124db68..2f5e32b --- a/linux-core/i915_drv.c +++ b/linux-core/i915_drv.c @@@ -309,8 -533,11 +534,10 @@@ static struct drm_driver driver = DRIVER_IRQ_VBL2, .load = i915_driver_load, .unload = i915_driver_unload, - .firstopen = i915_driver_firstopen, .lastclose = i915_driver_lastclose, .preclose = i915_driver_preclose, + .suspend = i915_suspend, + .resume = i915_resume, .device_is_agp = i915_driver_device_is_agp, .vblank_wait = i915_driver_vblank_wait, .vblank_wait2 = i915_driver_vblank_wait2, diff --cc shared-core/i915_dma.c index 07b3a35,18c3f0f..44a3d78 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@@ -78,10 -78,9 +78,8 @@@ void i915_kernel_lost_context(struct dr dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; } -static int i915_dma_cleanup(struct drm_device * dev) +int i915_dma_cleanup(struct drm_device * dev) { - struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private; - - drm_i915_private_t *dev_priv = dev->dev_private; /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. @@@ -92,11 -91,29 +90,9 @@@ return 0; } - static int i915_initialize(struct drm_device * dev, - struct drm_i915_private * dev_priv, - struct drm_i915_init * init) + static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) { - memset(dev_priv, 0, sizeof(struct drm_i915_private)); - drm_i915_private_t *dev_priv = dev->dev_private; ++ struct drm_i915_private *dev_priv = dev->dev_private; dev_priv->sarea = drm_getsarea(dev); if (!dev_priv->sarea) { @@@ -225,8 -237,7 +216,7 @@@ static int i915_dma_resume(struct drm_d static int i915_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv) { - struct drm_i915_private *dev_priv; - drm_i915_init_t *init = data; + struct drm_i915_init *init = data; int retcode = 0; switch (init->func) { diff --cc shared-core/i915_drv.h index be3212d,6ff34eb..02d0ba3 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@@ -147,70 -143,88 +147,93 @@@ struct drm_i915_private #endif DRM_SPINTYPE swaps_lock; - drm_i915_vbl_swap_t vbl_swaps; + struct drm_i915_vbl_swap vbl_swaps; unsigned int swaps_pending; + /* LVDS info */ + int backlight_duty_cycle; /* restore backlight to this value */ + bool panel_wants_dither; + struct drm_display_mode *panel_fixed_mode; + - /* Register state */ - u32 saveDSPACNTR; - u32 saveDSPBCNTR; - u32 savePIPEACONF; - u32 savePIPEBCONF; - u32 savePIPEASRC; - u32 savePIPEBSRC; - u32 saveFPA0; - u32 saveFPA1; - u32 saveDPLL_A; - u32 saveDPLL_A_MD; - u32 saveHTOTAL_A; - u32 saveHBLANK_A; - u32 saveHSYNC_A; - u32 saveVTOTAL_A; - u32 saveVBLANK_A; - u32 saveVSYNC_A; - u32 saveDSPASTRIDE; - u32 saveDSPASIZE; - u32 saveDSPAPOS; - u32 saveDSPABASE; - u32 saveDSPASURF; - u32 saveFPB0; - u32 saveFPB1; - u32 saveDPLL_B; - u32 saveDPLL_B_MD; - u32 saveHTOTAL_B; - u32 saveHBLANK_B; - u32 saveHSYNC_B; - u32 saveVTOTAL_B; - u32 saveVBLANK_B; - u32 saveVSYNC_B; - u32 saveDSPBSTRIDE; - u32 saveDSPBSIZE; - u32 saveDSPBPOS; - u32 saveDSPBBASE; - u32 saveDSPBSURF; - u32 saveVCLK_DIVISOR_VGA0; - u32 saveVCLK_DIVISOR_VGA1; - u32 saveVCLK_POST_DIV; - u32 saveVGACNTRL; - u32 saveADPA; - u32 saveLVDS; - u32 saveDVOA; - u32 saveDVOB; - u32 saveDVOC; - u32 savePP_ON; - u32 savePP_OFF; - u32 savePP_CONTROL; - u32 savePP_CYCLE; - u32 savePFIT_CONTROL; - u32 savePaletteA[256]; - u32 savePaletteB[256]; - u32 saveSWF[17]; + /* Register state */ + u8 saveLBB; + u32 saveDSPACNTR; + u32 saveDSPBCNTR; + u32 savePIPEACONF; + u32 savePIPEBCONF; + u32 savePIPEASRC; + u32 savePIPEBSRC; + u32 saveFPA0; + u32 saveFPA1; + u32 saveDPLL_A; + u32 saveDPLL_A_MD; + u32 saveHTOTAL_A; + u32 saveHBLANK_A; + u32 saveHSYNC_A; + u32 saveVTOTAL_A; + u32 saveVBLANK_A; + u32 saveVSYNC_A; + u32 saveBCLRPAT_A; + u32 saveDSPASTRIDE; + u32 saveDSPASIZE; + u32 saveDSPAPOS; + u32 saveDSPABASE; + u32 saveDSPASURF; + u32 saveDSPATILEOFF; + u32 savePFIT_PGM_RATIOS; u32 saveBLC_PWM_CTL; + u32 saveBLC_PWM_CTL2; + u32 saveFPB0; + u32 saveFPB1; + u32 saveDPLL_B; + u32 saveDPLL_B_MD; + u32 saveHTOTAL_B; + u32 saveHBLANK_B; + u32 saveHSYNC_B; + u32 saveVTOTAL_B; + u32 saveVBLANK_B; + u32 saveVSYNC_B; + u32 saveBCLRPAT_B; + u32 saveDSPBSTRIDE; + u32 saveDSPBSIZE; + u32 saveDSPBPOS; + u32 saveDSPBBASE; + u32 saveDSPBSURF; + u32 saveDSPBTILEOFF; + u32 saveVCLK_DIVISOR_VGA0; + u32 saveVCLK_DIVISOR_VGA1; + u32 saveVCLK_POST_DIV; + u32 saveVGACNTRL; + u32 saveADPA; + u32 saveLVDS; + u32 saveLVDSPP_ON; + u32 saveLVDSPP_OFF; + u32 saveDVOA; + u32 saveDVOB; + u32 saveDVOC; + u32 savePP_ON; + u32 savePP_OFF; + u32 savePP_CONTROL; + u32 savePP_CYCLE; + u32 savePFIT_CONTROL; + u32 save_palette_a[256]; + u32 save_palette_b[256]; + u32 saveFBC_CFB_BASE; + u32 saveFBC_LL_BASE; + u32 saveFBC_CONTROL; + u32 saveFBC_CONTROL2; + u32 saveSWF0[16]; + u32 saveSWF1[16]; + u32 saveSWF2[3]; + u8 saveMSR; + u8 saveSR[8]; + u8 saveGR[24]; + u8 saveAR_INDEX; + u8 saveAR[20]; + u8 saveDACMASK; + u8 saveDACDATA[256*3]; /* 256 3-byte colors */ + u8 saveCR[36]; -} drm_i915_private_t; +}; enum intel_chip_family { CHIP_I8XX = 0x01, @@@ -300,15 -310,14 +323,20 @@@ extern int i915_init_mem_type(struct dr extern uint32_t i915_evict_mask(struct drm_buffer_object *bo); extern int i915_move(struct drm_buffer_object *bo, int evict, int no_wait, struct drm_bo_mem_reg *new_mem); + void i915_flush_ttm(struct drm_ttm *ttm); + #endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) + extern void intel_init_chipset_flush_compat(struct drm_device *dev); + extern void intel_fini_chipset_flush_compat(struct drm_device *dev); #endif + +/* modesetting */ +extern void intel_modeset_init(struct drm_device *dev); +extern void intel_modeset_cleanup(struct drm_device *dev); + + #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) @@@ -346,31 -355,52 +374,75 @@@ I915_WRITE(LP_RING + RING_TAIL, outring); \ } while(0) +#define MI_NOOP (0x00 << 23) + extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); +/* + * The Bridge device's PCI config space has information about the + * fb aperture size and the amount of pre-reserved memory. + */ +#define INTEL_GMCH_CTRL 0x52 +#define INTEL_GMCH_ENABLED 0x4 +#define INTEL_GMCH_MEM_MASK 0x1 +#define INTEL_GMCH_MEM_64M 0x1 +#define INTEL_GMCH_MEM_128M 0 + +#define INTEL_855_GMCH_GMS_MASK (0x7 << 4) +#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) +#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) +#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) +#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) +#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) +#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) + +#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) +#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) + + /* Extended config space */ + #define LBB 0xf4 + + /* VGA stuff */ + + #define VGA_ST01_MDA 0x3ba + #define VGA_ST01_CGA 0x3da + + #define VGA_MSR_WRITE 0x3c2 + #define VGA_MSR_READ 0x3cc + #define VGA_MSR_MEM_EN (1<<1) + #define VGA_MSR_CGA_MODE (1<<0) + + #define VGA_SR_INDEX 0x3c4 + #define VGA_SR_DATA 0x3c5 + + #define VGA_AR_INDEX 0x3c0 + #define VGA_AR_VID_EN (1<<5) + #define VGA_AR_DATA_WRITE 0x3c0 + #define VGA_AR_DATA_READ 0x3c1 + + #define VGA_GR_INDEX 0x3ce + #define VGA_GR_DATA 0x3cf + /* GR05 */ + #define VGA_GR_MEM_READ_MODE_SHIFT 3 + #define VGA_GR_MEM_READ_MODE_PLANE 1 + /* GR06 */ + #define VGA_GR_MEM_MODE_MASK 0xc + #define VGA_GR_MEM_MODE_SHIFT 2 + #define VGA_GR_MEM_A0000_AFFFF 0 + #define VGA_GR_MEM_A0000_BFFFF 1 + #define VGA_GR_MEM_B0000_B7FFF 2 + #define VGA_GR_MEM_B0000_BFFFF 3 + + #define VGA_DACMASK 0x3c6 + #define VGA_DACRX 0x3c7 + #define VGA_DACWX 0x3c8 + #define VGA_DACDATA 0x3c9 + + #define VGA_CR_INDEX_MDA 0x3b4 + #define VGA_CR_DATA_MDA 0x3b5 + #define VGA_CR_INDEX_CGA 0x3d4 + #define VGA_CR_DATA_CGA 0x3d5 + #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) #define CMD_REPORT_HEAD (7<<23) @@@ -393,8 -423,37 +465,39 @@@ #define BB1_UNPROTECTED (0<<0) #define BB2_END_ADDR_MASK (~0x7) +#define I915REG_HWS_PGA 0x02080 + + /* Framebuffer compression */ + #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ + #define FBC_LL_BASE 0x03204 /* 4k page aligned */ + #define FBC_CONTROL 0x03208 + #define FBC_CTL_EN (1<<31) + #define FBC_CTL_PERIODIC (1<<30) + #define FBC_CTL_INTERVAL_SHIFT (16) + #define FBC_CTL_UNCOMPRESSIBLE (1<<14) + #define FBC_CTL_STRIDE_SHIFT (5) + #define FBC_CTL_FENCENO (1<<0) + #define FBC_COMMAND 0x0320c + #define FBC_CMD_COMPRESS (1<<0) + #define FBC_STATUS 0x03210 + #define FBC_STAT_COMPRESSING (1<<31) + #define FBC_STAT_COMPRESSED (1<<30) + #define FBC_STAT_MODIFIED (1<<29) + #define FBC_STAT_CURRENT_LINE (1<<0) + #define FBC_CONTROL2 0x03214 + #define FBC_CTL_FENCE_DBL (0<<4) + #define FBC_CTL_IDLE_IMM (0<<2) + #define FBC_CTL_IDLE_FULL (1<<2) + #define FBC_CTL_IDLE_LINE (2<<2) + #define FBC_CTL_IDLE_DEBUG (3<<2) + #define FBC_CTL_CPU_FENCE (1<<1) + #define FBC_CTL_PLANEA (0<<0) + #define FBC_CTL_PLANEB (1<<0) + #define FBC_FENCE_OFF 0x0321b + + #define FBC_LL_SIZE (1536) + #define FBC_LL_PAD (32) + /* Interrupt bits: */ #define USER_INT_FLAG (1<<1) @@@ -684,6 -678,8 +787,9 @@@ #define BLC_PWM_CTL 0x61254 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) + + #define BLC_PWM_CTL2 0x61250 ++ /** * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. @@@ -1099,35 -1119,13 +1229,17 @@@ */ #define SWF0 0x71410 +#define SWF1 0x71414 +#define SWF2 0x71418 +#define SWF3 0x7141c +#define SWF4 0x71420 +#define SWF5 0x71424 +#define SWF6 0x71428 --/* -- * 855 scratch registers. -- */ - #define SWF00 0x70410 - #define SWF01 0x70414 - #define SWF02 0x70418 - #define SWF03 0x7041c - #define SWF04 0x70420 - #define SWF05 0x70424 - #define SWF06 0x70428 - - #define SWF10 SWF0 - #define SWF11 SWF1 - #define SWF12 SWF2 - #define SWF13 SWF3 - #define SWF14 SWF4 - #define SWF15 SWF5 - #define SWF16 SWF6 - + #define SWF10 0x70410 - #define SWF30 0x72414 +#define SWF31 0x72418 +#define SWF32 0x7241c /* * Overlay registers. These are overlay registers accessed via MMIO.