From: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed, 14 Aug 2013 21:21:16 +0000 (-0700)
Subject: assembler: error for the wrong syntax of SEND instruction on GEN6+
X-Git-Tag: intel-gpu-tools-1.4~202
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=62298329350b965e4bbfc558e5a4b1b3646742ea;p=profile%2Fextras%2Fintel-gpu-tools.git

assembler: error for the wrong syntax of SEND instruction on GEN6+

   predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions
   predicate SEND execsize dst sendleadreg payload imm32reg instoptions
   predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions
   predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions

The above four syntaxes are only used on legacy platforms which support implied move
from payload to dst.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---

diff --git a/assembler/gram.y b/assembler/gram.y
index 09f21f1..9673eeb 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -1169,6 +1169,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload directsrcoperand instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  memset(&$$, 0, sizeof($$));
 		  set_instruction_opcode(&$$, $2);
 		  GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */
@@ -1187,6 +1190,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		  }
 		| predicate sendop execsize dst sendleadreg payload imm32reg instoptions
                 {
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
 		      $7.reg.type != BRW_REGISTER_TYPE_D &&
 		      $7.reg.type != BRW_REGISTER_TYPE_V) {
@@ -1290,6 +1296,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  if ($8.reg.type != BRW_REGISTER_TYPE_UD &&
 		      $8.reg.type != BRW_REGISTER_TYPE_D &&
 		      $8.reg.type != BRW_REGISTER_TYPE_V) {
@@ -1316,6 +1325,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload exp directsrcoperand instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  memset(&$$, 0, sizeof($$));
 		  set_instruction_opcode(&$$, $2);
 		  GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */