From: Komal Bajaj <quic_kbajaj@quicinc.com>
Date: Mon, 13 Mar 2023 12:57:31 +0000 (+0530)
Subject: arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller
X-Git-Tag: v6.6.17~5054^2~12^2~53
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6209038f131fee84ff1536dc59864f54d06740f2;p=platform%2Fkernel%2Flinux-rpi.git

arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller

Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313125731.17745-1-quic_kbajaj@quicinc.com
---

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 99d7840..7344381 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1321,6 +1321,18 @@
 			qcom,bcm-voters = <&apps_bcm_voter>;
 			#interconnect-cells = <2>;
 		};
+
+		system-cache-controller@19200000 {
+			compatible = "qcom,qdu1000-llcc";
+			reg = <0 0x19200000 0 0xd80000>,
+			      <0 0x1a200000 0 0x80000>,
+			      <0 0x221c8128 0 0x4>;
+			reg-names = "llcc_base",
+				    "llcc_broadcast_base",
+				    "multi_channel_register";
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			multi-ch-bit-off = <24 2>;
+		};
 	};
 
 	timer {