From: Lucas De Marchi Date: Wed, 9 Dec 2020 04:52:44 +0000 (-0800) Subject: drm/i915/gt: stop ignoring read with wa_masked_field_set X-Git-Tag: accepted/tizen/unified/20230118.172025~7733^2~20^2~105 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=61b3b0d1009986895be57b760ca4ebda43a212e2;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/gt: stop ignoring read with wa_masked_field_set When using masked registers, there is nothing to clear since a masked register has the mask in the upper 16b: we can just write to the location we want and use the mask to control what bits we are writing to. However that doesn't mean we don't want to read back the register and check the value actually matched what we wanted to write, i.e. that the WA stick. That should be an explicit opt-out for registers that are either write-only or that are affected by hardware misbehavior. Moreover both wa_masked_en() and wa_masked_dis() check the WA stick, so skipping the check just because the field is more than 1 bit is surprising and error-prone. Signed-off-by: Lucas De Marchi Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20201209045246.2905675-1-lucas.demarchi@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2db1e68..70d4ca2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -233,7 +233,7 @@ static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) { - wa_write_masked_or(wal, reg, 0, _MASKED_FIELD(mask, val)); + wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask); } static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,