From: Neil Armstrong Date: Mon, 25 Mar 2019 14:18:14 +0000 (+0100) Subject: drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clock X-Git-Tag: v5.15~303^2~28^2~5473 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=61af6e22ec265849133bdfc4058bf0f1b28c5c24;p=platform%2Fkernel%2Flinux-starfive.git drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clock On Amlogic G12A SoC, the 2,97GHz PLL frequency is not stable enough to provide a correct 297MHz pixel clock, so switch the PLL base frequency with a /2 OD when the 297MHz pixel clock is requested. This solves the issue on G12A and also works fine on GXBB, GXL & GXM. Signed-off-by: Neil Armstrong Tested-by: Jerome Brunet Reviewed-by: Jerome Brunet Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-2-narmstrong@baylibre.com --- diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index f6ba35a..c15a5a5 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -396,8 +396,8 @@ struct meson_vclk_params { }, [MESON_VCLK_HDMI_297000] = { .pixel_freq = 297000, - .pll_base_freq = 2970000, - .pll_od1 = 1, + .pll_base_freq = 5940000, + .pll_od1 = 2, .pll_od2 = 1, .pll_od3 = 1, .vid_pll_div = VID_PLL_DIV_5,