From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Fri, 20 Jan 2023 00:39:53 +0000 (-0800)
Subject: Merge patch series "Putting some basic order on isa extension lists"
X-Git-Tag: v6.6.17~5433^2~28
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=61a9b7129070e07c207d89fffbce577223507327;p=platform%2Fkernel%2Flinux-rpi.git

Merge patch series "Putting some basic order on isa extension lists"

This cleans up the ISA string handling to more closely match a version
of the ISA spec.  This is visible in /proc/cpuinfo and the ordering
changes may break something in userspace, but these orderings have
changed before without issues so with any luck that's still the case.

This also adds documentation so userspace has a better idea of what is
intended when it comes to compatibility for /proc/cpuinfo, which should
help everyone as this will likely keep changing.

* b4-shazam-merge:
  Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo
  RISC-V: resort all extensions in consistent orders
  RISC-V: clarify ISA string ordering rules in cpu.c

Link: https://lore.kernel.org/r/20221205144525.2148448-1-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

61a9b7129070e07c207d89fffbce577223507327
diff --cc arch/riscv/include/asm/hwcap.h
index 86328e3,ce522aad..57439da
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -57,11 -60,8 +60,9 @@@ enum riscv_isa_ext_id 
  	RISCV_ISA_EXT_SVPBMT,
  	RISCV_ISA_EXT_ZICBOM,
  	RISCV_ISA_EXT_ZIHINTPAUSE,
- 	RISCV_ISA_EXT_SSTC,
- 	RISCV_ISA_EXT_SVINVAL,
 -	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
 +	RISCV_ISA_EXT_ID_MAX
  };
 +static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
  
  /*
   * This enum represents the logical ID for each RISC-V ISA extension static
diff --cc arch/riscv/kernel/cpufeature.c
index 205bbd6,8a76a6c..dde0e91
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@@ -215,14 -196,13 +215,17 @@@ void __init riscv_fill_hwcap(void
  			if (unlikely(ext_err))
  				continue;
  			if (!ext_long) {
 -				this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
 -				set_bit(*ext - 'a', this_isa);
 +				int nr = *ext - 'a';
 +
 +				if (riscv_isa_extension_check(nr)) {
 +					this_hwcap |= isa2hwcap[nr];
 +					set_bit(nr, this_isa);
 +				}
  			} else {
+ 				/* sorted alphabetically */
  				SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
+ 				SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
+ 				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
  				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
  				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
  				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);