From: kele bai <kele.bai@amlogic.com>
Date: Fri, 2 Mar 2018 07:17:05 +0000 (+0800)
Subject: di: G12A add di nrds&pps&diwr support
X-Git-Tag: khadas-vims-v0.9.6-release~2474
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=616cd64cd67354981e8cfd930aac49b827678b12;p=platform%2Fkernel%2Flinux-amlogic.git

di: G12A add di nrds&pps&diwr support

PD#156734: G12A add di nrds&pps&diwr support

1) move hdr&vd1&viu releated reg into di_regs.h
2) delete unuseful reg definition
3) add pps in post function
4) add new framereset

Change-Id: I49c58072cc90aa556ab368dcc616c3be4a692db4
Signed-off-by: kele bai <kele.bai@amlogic.com>
---

diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
index 0a5078e..6854f1f 100644
--- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
@@ -92,7 +92,7 @@
 			 * 10x4736064=45.2M(0x2e) support 12bit
 			 * 10x4074560=40M(0x28) support 10bit
 			 */
-			size = <0x0 0x02900000>;
+			size = <0x0 0x02800000>;
 			alignment = <0x0 0x400000>;
 		};
 		codec_mm_cma:linux,codec_mm_cma {
diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c
index 441716d..21bfe55 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace.c
@@ -76,6 +76,10 @@
 #define CLASS_NAME		"deinterlace"
 #define VFM_NAME		"deinterlace"
 
+static struct di_pre_stru_s di_pre_stru;
+
+static struct di_post_stru_s di_post_stru;
+
 static DEFINE_SPINLOCK(di_lock2);
 
 #define di_lock_irqfiq_save(irq_flag) \
@@ -138,6 +142,7 @@ static int timeout_miss_policy;
  */
 
 static int force_width;
+static int force_height;
 /* add avoid vframe put/get error */
 static int di_blocking;
 /*
@@ -376,8 +381,10 @@ void DI_VSYNC_WR_MPEG_REG(unsigned int addr, unsigned int val)
 {
 	if (is_need_stop_reg(addr))
 		return;
-
-	VSYNC_WR_MPEG_REG(addr, val);
+	if (post_wr_en && post_wr_support)
+		DI_Wr(addr, val);
+	else
+		VSYNC_WR_MPEG_REG(addr, val);
 }
 
 void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, unsigned int val,
@@ -385,8 +392,10 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, unsigned int val,
 {
 	if (is_need_stop_reg(addr))
 		return;
-
-	VSYNC_WR_MPEG_REG_BITS(addr, val, start, len);
+	if (post_wr_en && post_wr_support)
+		DI_Wr_reg_bits(addr, val, start, len);
+	else
+		VSYNC_WR_MPEG_REG_BITS(addr, val, start, len);
 }
 
 unsigned int DI_POST_REG_RD(unsigned int addr)
@@ -459,7 +468,6 @@ store_dbg(struct device *dev,
 		dump_vframe(vf);
 	} else if (strncmp(buf, "pool", 4) == 0) {
 		unsigned long idx = 0;
-
 		if (kstrtoul(buf + 4, 10, &idx))
 			return count;
 		dump_pool(get_queue_by_idx(idx));
@@ -494,8 +502,8 @@ store_dbg(struct device *dev,
 			dump_di_reg_g12();
 		else
 			dump_di_reg();
-	} else if (strncmp(buf, "robust_test", 11) == 0) {
-		recovery_flag = 1;
+	} else if (strncmp(buf, "dump_mif", 8) == 0) {
+		dump_mif_size_state(&di_pre_stru, &di_post_stru);
 	} else if (strncmp(buf, "recycle_buf", 11) == 0) {
 		recycle_keep_buffer();
 	} else if (strncmp(buf, "recycle_post", 12) == 0) {
@@ -1164,9 +1172,6 @@ static bool is_in_queue(struct di_buf_s *di_buf, int queue_idx)
 	return ret;
 }
 
-static struct di_pre_stru_s di_pre_stru;
-
-static struct di_post_stru_s di_post_stru;
 
 
 static ssize_t
@@ -1176,6 +1181,7 @@ store_dump_mem(struct device *dev, struct device_attribute *attr,
 	unsigned int n = 0, canvas_w = 0, canvas_h = 0;
 	unsigned long nr_size = 0, dump_adr = 0;
 	struct di_buf_s *di_buf = NULL;
+	struct vframe_s *post_vf = NULL;
 	char *buf_orig, *ps, *token;
 	char *parm[3] = { NULL };
 	char delim1[2] = " ";
@@ -1200,9 +1206,16 @@ store_dump_mem(struct device *dev, struct device_attribute *attr,
 	}
 	if (strcmp(parm[0], "capture") == 0)
 		di_buf = di_pre_stru.di_mem_buf_dup_p;
-	else if (strcmp(parm[0], "capture_post") == 0)
-		di_buf = di_post_stru.cur_post_buf;
-	else if (strcmp(parm[0], "capture_nrds") == 0)
+	else if (strcmp(parm[0], "capture_post") == 0) {
+		if (di_vf_peek(NULL)) {
+			post_vf = di_vf_get(NULL);
+			if (!IS_ERR_OR_NULL(post_vf)) {
+				di_buf = post_vf->private_data;
+				di_vf_put(post_vf, NULL);
+			}
+			post_vf = NULL;
+		}
+	} else if (strcmp(parm[0], "capture_nrds") == 0)
 		get_nr_ds_buf(&dump_adr, &nr_size);
 	else {
 		pr_err("wrong dump cmd\n");
@@ -1305,12 +1318,8 @@ static void dis2_di(void)
 		}
 	}
 
-	if (post_wr_en && post_wr_support) {
+	if (post_wr_en && post_wr_support)
 		diwr_set_power_control(0);
-		#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
-		enable_rdma(1);
-		#endif
-	}
 
 	di_unlock_irqfiq_restore(irq_flag2);
 	spin_unlock_irqrestore(&plist_lock, flags);
@@ -1938,6 +1947,8 @@ static int di_init_buf(int width, int height, unsigned char prog_flag)
 			di_buf_size = nr_size + mtn_size + count_size;
 		}
 		di_buf_size = roundup(di_buf_size, PAGE_SIZE);
+		pr_info("[DI] %s buffer size %u.\n", __func__,
+			di_buf_size);
 		de_devp->buf_num_avail = de_devp->mem_size / di_buf_size;
 
 		if (post_wr_en && post_wr_support) {
@@ -2396,7 +2407,7 @@ config_di_mcinford_mif(struct DI_MC_MIF_s *di_mcinford_mif,
 		       struct di_buf_s *di_buf)
 {
 	if (di_buf) {
-		di_mcinford_mif->size_x = di_buf->vframe->height / 4 - 1;
+		di_mcinford_mif->size_x = (di_buf->vframe->height + 2) / 4 - 1;
 		di_mcinford_mif->size_y = 1;
 		di_mcinford_mif->canvas_num = di_buf->mcinfo_canvas_idx;
 	}
@@ -2406,13 +2417,17 @@ config_di_pre_mc_mif(struct DI_MC_MIF_s *di_mcinfo_mif,
 		     struct DI_MC_MIF_s *di_mcvec_mif,
 		     struct di_buf_s *di_buf)
 {
+	unsigned int pre_size_w = 0, pre_size_h = 0;
+
 	if (di_buf) {
-		di_mcinfo_mif->size_x = di_buf->vframe->height / 4 - 1;
+		pre_size_w = di_buf->vframe->width;
+		pre_size_h = (di_buf->vframe->height + 1) / 2;
+		di_mcinfo_mif->size_x = (pre_size_h + 1) / 2 - 1;
 		di_mcinfo_mif->size_y = 1;
 		di_mcinfo_mif->canvas_num = di_buf->mcinfo_canvas_idx;
 
-		di_mcvec_mif->size_x = (di_buf->vframe->width + 4) / 5 - 1;
-		di_mcvec_mif->size_y = di_buf->vframe->height / 2 - 1;
+		di_mcvec_mif->size_x = (pre_size_w + 4) / 5 - 1;
+		di_mcvec_mif->size_y = pre_size_h - 1;
 		di_mcvec_mif->canvas_num = di_buf->mcvec_canvas_idx;
 	}
 }
@@ -2700,6 +2715,7 @@ static void pre_de_process(void)
 			nr_ds_hw_ctrl(false);
 		}
 	}
+
 	/* set interrupt mask for pre module.
 	 * we need to only leave one mask open
 	 * to prevent multiple entry for de_irq
@@ -2761,27 +2777,21 @@ static void pre_de_process(void)
 			vdin_ops->tvin_vdin_func(0, &vdin_arg);
 	}
 #endif
-#if 0
+	enable_di_pre_mif(true, mcpre_en);
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
 		RDMA_WR(DI_PRE_GL_CTRL, 0xc3200005);
 		RDMA_WR(DI_PRE_GL_CTRL, 0x83200005);
+		reset_pre_simple_mif();
 	} else {
 		/* frame + soft reset for the pre modules. */
 		RDMA_WR(DI_PRE_CTRL, Rd(DI_PRE_CTRL) | 3 << 30);
+		/* enable mc pre mif*/
+		enable_di_pre_mif(true, mcpre_en);
 	}
-#endif
-	enable_di_pre_mif(true, mcpre_en);
-
-	/* frame + soft reset for the pre modules. */
-	RDMA_WR_BITS(DI_PRE_CTRL, 3, 30, 2);
-
 	#ifdef SUPPORT_MPEG_TO_VDIN
 	if (mpeg2vdin_flag)
 		RDMA_WR_BITS(DI_PRE_CTRL, 1, 13, 1);
 	#endif
-
-	/* enable mc pre mif*/
-	enable_di_pre_mif(true, mcpre_en);
 	di_pre_stru.irq_time = sched_clock()/NSEC_PER_MSEC;
 #ifdef CONFIG_AMLOGIC_MEDIA_RDMA
 	if (di_pre_rdma_enable & 0x2)
@@ -3177,6 +3187,8 @@ static int pps_dsth;
 module_param_named(pps_dsth, pps_dsth, int, 0644);
 static bool pps_en;
 module_param_named(pps_en, pps_en, bool, 0644);
+static unsigned int pps_position = 1;
+module_param_named(pps_position, pps_position, uint, 0644);
 static unsigned int pre_enable_mask = 3;
 module_param_named(pre_enable_mask, pre_enable_mask, uint, 0644);
 
@@ -3270,10 +3282,12 @@ jiffies_to_msecs(jiffies_64 - vframe->ready_jiffies64));
 							is_meson_gxl_cpu() ||
 							is_meson_gxm_cpu());
 		width_roundup = bit10_pack_patch ? 16 : width_roundup;
+#if 0 //test for even width&height
 		if (di_force_bit_mode == 10)
 			force_width = roundup(vframe->width, width_roundup);
 		else
 			force_width = 0;
+#endif
 		di_pre_stru.source_trans_fmt = vframe->trans_fmt;
 		di_pre_stru.left_right = di_pre_stru.left_right ? 0 : 1;
 		di_pre_stru.invert_flag =
@@ -3296,6 +3310,9 @@ jiffies_to_msecs(jiffies_64 - vframe->ready_jiffies64));
 		di_pre_stru.width_bk = vframe->width;
 		if (force_width)
 			vframe->width = force_width;
+		if (force_height)
+			vframe->height = force_height;
+
 		/* backup frame motion info */
 		vframe->combing_cur_lev = cur_lev;
 
@@ -3668,7 +3685,7 @@ jiffies_to_msecs(jiffies_64 - vframe->ready_jiffies64));
 	/* set vframe bit info */
 	di_buf->vframe->bitdepth &= ~(BITDEPTH_YMASK);
 	di_buf->vframe->bitdepth &= ~(FULL_PACK_422_MODE);
-	if (de_devp->pps_enable || pps_en) {
+	if (de_devp->pps_enable && pps_position) {
 		if (pps_dstw != di_buf->vframe->width) {
 			di_buf->vframe->width = pps_dstw;
 			di_pre_stru.width_bk = pps_dstw;
@@ -4507,10 +4524,19 @@ de_post_process(void *arg, unsigned int zoom_start_x_lines,
 		di_post_stru.di_buf2_mif.luma_x_end0 = di_end_x;
 
 		if (post_wr_en && post_wr_support) {
-			di_post_stru.di_diwr_mif.start_x = di_start_x;
-			di_post_stru.di_diwr_mif.end_x   = di_end_x;
-			di_post_stru.di_diwr_mif.start_y = di_start_y;
-			di_post_stru.di_diwr_mif.end_y   = di_end_y;
+			if (de_devp->pps_enable && pps_position == 0) {
+				di_pps_config(0, di_width, di_height,
+					pps_dstw, pps_dsth);
+				di_post_stru.di_diwr_mif.start_x = 0;
+				di_post_stru.di_diwr_mif.end_x   = pps_dstw - 1;
+				di_post_stru.di_diwr_mif.start_y = 0;
+				di_post_stru.di_diwr_mif.end_y   = pps_dsth - 1;
+			} else {
+				di_post_stru.di_diwr_mif.start_x = di_start_x;
+				di_post_stru.di_diwr_mif.end_x   = di_end_x;
+				di_post_stru.di_diwr_mif.start_y = di_start_y;
+				di_post_stru.di_diwr_mif.end_y   = di_end_y;
+			}
 		}
 
 		di_post_stru.di_mtnprd_mif.start_x = di_start_x;
@@ -4871,6 +4897,10 @@ static void post_de_done_buf_config(void)
 	di_lock_irqfiq_save(irq_flag2);
 	queue_out(di_post_stru.cur_post_buf);
 	di_buf = di_post_stru.cur_post_buf;
+	if (de_devp->pps_enable && pps_position == 0) {
+		di_buf->vframe->width = pps_dstw;
+		di_buf->vframe->height = pps_dsth;
+	}
 	queue_in(di_post_stru.cur_post_buf, QUEUE_POST_READY);
 	di_unlock_irqfiq_restore(irq_flag2);
 	vf_notify_receiver(VFM_NAME, VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
@@ -5615,12 +5645,8 @@ static void di_unreg_process_irq(void)
 				VPU_CLK_GATE_OFF);
 			pr_info("%s disable di mirror image.\n", __func__);
 	}
-	if (post_wr_en && post_wr_support) {
+	if (post_wr_en && post_wr_support)
 		diwr_set_power_control(0);
-		#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
-		enable_rdma(1);
-		#endif
-	}
 	di_unlock_irqfiq_restore(irq_flag2);
 
 #if (defined ENABLE_SPIN_LOCK_ALWAYS)
@@ -5738,13 +5764,11 @@ static void di_pre_size_change(unsigned short width,
 
 	di_load_pq_table();
 
-#if 0
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
 		RDMA_WR(DI_PRE_GL_CTRL, 0x80000005);
-#endif
 	if (de_devp->nrds_enable)
 		nr_ds_init(width, height);
-	if (de_devp->pps_enable || pps_en) {
+	if (de_devp->pps_enable && pps_position) {
 		pps_w = di_pre_stru.cur_width;
 		pps_h = di_pre_stru.cur_height>>(vf_type?1:0);
 		di_pps_config(1, pps_w, pps_h, pps_dstw, (pps_dsth>>1));
@@ -5824,12 +5848,8 @@ static void di_reg_process_irq(void)
 		de_devp->nrds_enable = nrds_en;
 		de_devp->pps_enable = pps_en;
 		switch_vpu_clk_gate_vmod(VPU_VPU_CLKB, VPU_CLK_GATE_ON);
-		if (post_wr_en && post_wr_support) {
+		if (post_wr_en && post_wr_support)
 			diwr_set_power_control(1);
-			#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
-			enable_rdma(0);
-			#endif
-		}
 		if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
 			if (!use_2_interlace_buff) {
 				#ifdef CLK_TREE_SUPPORT
@@ -6379,7 +6399,9 @@ light_unreg:
 		if (receiver_name) {
 			if (!strcmp(receiver_name, "amvideo")) {
 				di_post_stru.run_early_proc_fun_flag = 0;
-		/* pr_info("set run_early_proc_fun_flag to 1\n"); */
+				if (post_wr_en && post_wr_support)
+					di_post_stru.run_early_proc_fun_flag
+						= 1;
 			} else {
 				di_post_stru.run_early_proc_fun_flag = 1;
 				pr_info("set run_early_proc_fun_flag to 1\n");
@@ -6451,7 +6473,7 @@ static void fast_process(void)
 			while (process_post_vframe()) {
 				if (di_post_stru.di_post_process_cnt++ >
 					MAX_POST_BUF_NUM) {
-					di_pr_info("%s: process_post_vframe time out!!\n",
+					pr_info("%s: process_post_vframe time out!!\n",
 						__func__);
 					break;
 				}
@@ -7154,10 +7176,6 @@ static int di_probe(struct platform_device *pdev)
 	ret = of_property_read_u32(pdev->dev.of_node,
 		"pps-enable", &(di_devp->pps_enable));
 
-	pr_info("DI cma_flag %u, nrds %u, pps %u.\n",
-			di_devp->flag_cma,
-			di_devp->nrds_enable,
-			di_devp->pps_enable);
 	if (di_devp->flag_cma >= 1) {
 #ifdef CONFIG_CMA
 		di_devp->pdev = pdev;
@@ -7498,6 +7516,7 @@ module_param_named(bypass_trick_mode, bypass_trick_mode, int, 0664);
 module_param_named(invert_top_bot, invert_top_bot, int, 0664);
 module_param_named(skip_top_bot, skip_top_bot, int, 0664);
 module_param_named(force_width, force_width, int, 0664);
+module_param_named(force_height, force_height, int, 0664);
 module_param_named(prog_proc_config, prog_proc_config, int, 0664);
 module_param_named(start_frame_drop_count, start_frame_drop_count, int, 0664);
 #ifdef SUPPORT_START_FRAME_HOLD
@@ -7572,6 +7591,7 @@ module_param_named(queue_print_flag, queue_print_flag, int, 0664);
 module_param_named(full_422_pack, full_422_pack, bool, 0644);
 #ifdef DEBUG_SUPPORT
 module_param_named(pulldown_enable, pulldown_enable, bool, 0644);
+module_param_named(cma_print, cma_print, bool, 0644);
 #ifdef RUN_DI_PROCESS_IN_IRQ
 module_param_named(input2pre, input2pre, uint, 0664);
 module_param_named(input2pre_buf_miss_count, input2pre_buf_miss_count,
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_dbg.c b/drivers/amlogic/media/deinterlace/deinterlace_dbg.c
index 5ed3fd5..99e0d69 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_dbg.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_dbg.c
@@ -436,28 +436,6 @@ void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p)
 		di_pre_stru_p->bypass_pre ? "true" : "false");
 	pr_info("invert_flag	   = %s\n",
 		di_pre_stru_p->invert_flag ? "true" : "false");
-	pr_info("inp mif:\n");
-	dump_mif_state(&di_pre_stru_p->di_inp_mif);
-	pr_info("mem mif:\n");
-	dump_mif_state(&di_pre_stru_p->di_mem_mif);
-	pr_info("chan2 mif:\n");
-	dump_mif_state(&di_pre_stru_p->di_chan2_mif);
-	pr_info("nrwr mif:\n");
-	dump_simple_mif_state(&di_pre_stru_p->di_nrwr_mif);
-	pr_info("mtnwr mif:\n");
-	dump_simple_mif_state(&di_pre_stru_p->di_mtnwr_mif);
-	pr_info("contp2rd mif:\n");
-	dump_simple_mif_state(&di_pre_stru_p->di_contp2rd_mif);
-	pr_info("contprd mif:\n");
-	dump_simple_mif_state(&di_pre_stru_p->di_contprd_mif);
-	pr_info("contwr mif:\n");
-	dump_simple_mif_state(&di_pre_stru_p->di_contwr_mif);
-	pr_info("mcinford mif:\n");
-	dump_mc_mif_state(&di_pre_stru_p->di_mcinford_mif);
-	pr_info("mcinfowr mif:\n");
-	dump_mc_mif_state(&di_pre_stru_p->di_mcinfowr_mif);
-	pr_info("mcvecwr mif:\n");
-	dump_mc_mif_state(&di_pre_stru_p->di_mcvecwr_mif);
 }
 
 void dump_di_post_stru(struct di_post_stru_s *di_post_stru_p)
@@ -473,20 +451,67 @@ void dump_di_post_stru(struct di_post_stru_s *di_post_stru_p)
 		di_post_stru_p->de_post_process_done);
 	pr_info("cur_post_buf			= 0x%p\n,",
 		di_post_stru_p->cur_post_buf);
-	pr_info("if0 mif:\n");
-	dump_mif_state(&di_post_stru_p->di_buf0_mif);
-	pr_info("if1 mif:\n");
-	dump_mif_state(&di_post_stru_p->di_buf1_mif);
-	pr_info("if2 mif:\n");
-	dump_mif_state(&di_post_stru_p->di_buf2_mif);
-	pr_info("diwr mif:\n");
-	dump_simple_mif_state(&di_post_stru_p->di_diwr_mif);
-	pr_info("mtnprd mif:\n");
-	dump_simple_mif_state(&di_post_stru_p->di_mtnprd_mif);
-	pr_info("mcvecrd mif:\n");
-	dump_mc_mif_state(&di_post_stru_p->di_mcvecrd_mif);
 }
 
+void dump_mif_size_state(struct di_pre_stru_s *pre_stru_p,
+	struct di_post_stru_s *post_stru_p)
+{
+	pr_info("======pre mif status======\n");
+	pr_info("DI_PRE_SIZE=0x%x", Rd(DI_PRE_SIZE));
+	pr_info("DNR_HVSIZE=0x%x\n", Rd(DNR_HVSIZE));
+	pr_info("CONTWR_CAN_SIZE=0x%x", Rd(0x37ec));
+	pr_info("MTNWR_CAN_SIZE=0x%x\n", Rd(0x37f0));
+	pr_info("DNR_STAT_X_START_END=0x%x", Rd(0x2d08));
+	pr_info("DNR_STAT_Y_START_END=0x%x\n", Rd(0x2d09));
+	pr_info("MCDI_HV_SIZEIN=0x%x", Rd(0x2f00));
+	pr_info("MCDI_HV_BLKSIZEIN=0x%x\n", Rd(0x2f01));
+	pr_info("MCVECWR_CAN_SIZE=0x%x", Rd(0x37f4));
+	pr_info("MCINFWR_CAN_SIZE=0x%x\n", Rd(0x37f8));
+	pr_info("NRDSWR_CAN_SIZE=0x%x", Rd(0x37fc));
+	pr_info("NR_DS_BUF_SIZE=0x%x\n", Rd(0x3740));
+	pr_info("=====inp mif:\n");
+	dump_mif_state(&pre_stru_p->di_inp_mif);
+	pr_info("=====mem mif:\n");
+	dump_mif_state(&pre_stru_p->di_mem_mif);
+	pr_info("=====chan2 mif:\n");
+	dump_mif_state(&pre_stru_p->di_chan2_mif);
+	pr_info("=====nrwr mif:\n");
+	dump_simple_mif_state(&pre_stru_p->di_nrwr_mif);
+	pr_info("=====mtnwr mif:\n");
+	dump_simple_mif_state(&pre_stru_p->di_mtnwr_mif);
+	pr_info("=====contp2rd mif:\n");
+	dump_simple_mif_state(&pre_stru_p->di_contp2rd_mif);
+	pr_info("=====contprd mif:\n");
+	dump_simple_mif_state(&pre_stru_p->di_contprd_mif);
+	pr_info("=====contwr mif:\n");
+	dump_simple_mif_state(&pre_stru_p->di_contwr_mif);
+	pr_info("=====mcinford mif:\n");
+	dump_mc_mif_state(&pre_stru_p->di_mcinford_mif);
+	pr_info("=====mcinfowr mif:\n");
+	dump_mc_mif_state(&pre_stru_p->di_mcinfowr_mif);
+	pr_info("=====mcvecwr mif:\n");
+	dump_mc_mif_state(&pre_stru_p->di_mcvecwr_mif);
+	pr_info("======post mif status======\n");
+	pr_info("DI_POST_SIZE=0x%x", Rd(DI_POST_SIZE));
+	pr_info("DECOMB_FRM_SIZE=0x%x\n", Rd(0x2d8f));
+	pr_info("=====if0 mif:\n");
+	dump_mif_state(&post_stru_p->di_buf0_mif);
+	pr_info("=====if1 mif:\n");
+	dump_mif_state(&post_stru_p->di_buf1_mif);
+	pr_info("=====if2 mif:\n");
+	dump_mif_state(&post_stru_p->di_buf2_mif);
+	pr_info("=====diwr mif:\n");
+	dump_simple_mif_state(&post_stru_p->di_diwr_mif);
+	pr_info("=====mtnprd mif:\n");
+	dump_simple_mif_state(&post_stru_p->di_mtnprd_mif);
+	pr_info("=====mcvecrd mif:\n");
+	dump_mc_mif_state(&post_stru_p->di_mcvecrd_mif);
+	pr_info("======pps size status======\n");
+	pr_info("DI_SC_LINE_IN_LENGTH=0x%x", Rd(0x3751));
+	pr_info("DI_SC_PIC_IN_HEIGHT=0x%x\n", Rd(0x3752));
+	pr_info("DI_HDR_IN_HSIZE=0x%x", Rd(0x376e));
+	pr_info("DI_HDR_IN_VSIZE=0x%x\n", Rd(0x376f));
+}
 void dump_di_buf(struct di_buf_s *di_buf)
 {
 	pr_info("di_buf %p vframe %p:\n", di_buf, di_buf->vframe);
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_dbg.h b/drivers/amlogic/media/deinterlace/deinterlace_dbg.h
index 5174591..c45da23 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_dbg.h
+++ b/drivers/amlogic/media/deinterlace/deinterlace_dbg.h
@@ -30,6 +30,8 @@ void print_di_buf(struct di_buf_s *di_buf, int format);
 void dump_pre_mif_state(void);
 void dump_post_mif_reg(void);
 void dump_buf_addr(struct di_buf_s *di_buf, unsigned int num);
+void dump_mif_size_state(struct di_pre_stru_s *pre,
+struct di_post_stru_s *post);
 void debug_device_files_add(struct device *dev);
 void debug_device_files_del(struct device *dev);
 #endif
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
index 90d5a06..16e16c6 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
@@ -617,6 +617,8 @@ static void set_di_nrwr_mif(struct DI_SIM_MIF_s *nrwr_mif,
 	RDMA_WR_BITS(DI_NRWR_X,	nrwr_mif->start_x, 16, 14);
 	RDMA_WR_BITS(DI_NRWR_Y, nrwr_mif->start_y, 16, 13);
 	RDMA_WR_BITS(DI_NRWR_Y, nrwr_mif->end_y, 0, 13);
+	/* wr ext en from gxtvbb */
+	RDMA_WR_BITS(DI_NRWR_Y, 1, 15, 1);
 	RDMA_WR_BITS(DI_NRWR_Y, 3, 30, 2);
 	RDMA_WR(DI_NRWR_CTRL, nrwr_mif->canvas_num|
 			(urgent<<16)|
@@ -651,16 +653,28 @@ void enable_di_pre_aml(
 	set_di_nrwr_mif(di_nrwr_mif, pre_urgent);
 	set_di_mem_mif(di_mem_mif, pre_urgent, pre_hold_line);
 	set_di_chan2_mif(di_chan2_mif, pre_urgent, pre_hold_line);
-	nrwr_hsize = di_nrwr_mif->end_x - di_nrwr_mif->start_x;
-	nrwr_vsize = di_nrwr_mif->end_y - di_nrwr_mif->start_y;
-	chan2_hsize = di_chan2_mif->luma_x_start0 - di_chan2_mif->luma_x_end0;
-	chan2_vsize = di_chan2_mif->luma_y_start0 - di_chan2_mif->luma_y_end0;
-	mem_hsize = di_mem_mif->luma_x_start0 - di_mem_mif->luma_x_end0;
-	mem_vsize = di_mem_mif->luma_y_start0 - di_mem_mif->luma_y_end0;
-	if ((chan2_hsize < nrwr_hsize) || (chan2_vsize < nrwr_vsize))
+
+	nrwr_hsize = di_nrwr_mif->end_x -
+		di_nrwr_mif->start_x + 1;
+	nrwr_vsize = di_nrwr_mif->end_y -
+		di_nrwr_mif->start_y + 1;
+	chan2_hsize = di_chan2_mif->luma_x_end0 -
+		di_chan2_mif->luma_x_start0 + 1;
+	chan2_vsize = di_chan2_mif->luma_y_end0 -
+		di_chan2_mif->luma_y_start0 + 1;
+	mem_hsize = di_mem_mif->luma_x_end0 -
+		di_mem_mif->luma_x_start0 + 1;
+	mem_vsize = di_mem_mif->luma_y_end0 -
+		di_mem_mif->luma_y_start0 + 1;
+
+	if ((chan2_hsize != nrwr_hsize) || (chan2_vsize != nrwr_vsize)) {
 		chan2_disable = true;
-	if ((mem_hsize < nrwr_hsize) || (mem_vsize < nrwr_vsize))
+		pr_info("[DI] pre size not match bypass chan2.\n");
+	}
+	if ((mem_hsize != nrwr_hsize) || (mem_vsize != nrwr_vsize)) {
 		mem_bypass = true;
+		pr_info("[DI] pre size not match bypass mem.\n");
+	}
 
 	if (madi_en) {
 		/*
@@ -747,6 +761,22 @@ void enable_di_pre_aml(
 				   );
 	}
 }
+/*
+ * after g12a, framereset will not reset simple
+ * wr mif of pre such as mtn&cont&mv&mcinfo wr
+ */
+void reset_pre_simple_mif(void)
+{
+	RDMA_WR_BITS(CONTWR_CAN_SIZE, 1, 14, 1);
+	RDMA_WR_BITS(MTNWR_CAN_SIZE, 1, 14, 1);
+	RDMA_WR_BITS(MCVECWR_CAN_SIZE, 1, 14, 1);
+	RDMA_WR_BITS(MCINFWR_CAN_SIZE, 1, 14, 1);
+
+	RDMA_WR_BITS(CONTWR_CAN_SIZE, 0, 14, 1);
+	RDMA_WR_BITS(MTNWR_CAN_SIZE, 0, 14, 1);
+	RDMA_WR_BITS(MCVECWR_CAN_SIZE, 0, 14, 1);
+	RDMA_WR_BITS(MCINFWR_CAN_SIZE, 0, 14, 1);
+}
 
 void enable_afbc_input(struct vframe_s *vf)
 {
@@ -2061,23 +2091,20 @@ void initial_di_post_2(int hsize_post, int vsize_post,
 	DI_VSYNC_WR_MPEG_REG(DI_BLEND_REG2_X, (hsize_post-1));
 	DI_VSYNC_WR_MPEG_REG(DI_BLEND_REG3_X, (hsize_post-1));
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
-		#if 0
-		if (post_write_en)
-			DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x80000005);
-		else
-			DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x00200005);
-		#endif
 		if (post_write_en) {
-			DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
-				0, 8, 9);
+			DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x80000005);
 			DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
 				0, 20, 1);
-		} else {
 			DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
-				1, 8, 9);
+				0, 8, 9);
+		} else {
+			DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x00200005);
 			DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
 				1, 20, 1);
+			DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
+				1, 8, 9);
 		}
+
 	} else {
 		/* enable ma,disable if0 to vpp */
 		if ((VSYNC_RD_MPEG_REG(VIU_MISC_CTRL0) & 0x50000) != 0x50000) {
@@ -2094,8 +2121,8 @@ void initial_di_post_2(int hsize_post, int vsize_post,
 					  (0 << 4)	|
 					  (0 << 5)	|
 					  (0 << 6)	|
-					  (0 << 7)	|
-					  (1 << 8)	|
+					  ((post_write_en?1:0) << 7)	|
+					  ((post_write_en?0:1) << 8)	|
 					  (0 << 9)	|
 					  (0 << 10) |
 					  (0 << 11) |
@@ -2127,8 +2154,6 @@ module_param(pldn_ctrl_rflsh, uint, 0644);
 MODULE_PARM_DESC(pldn_ctrl_rflsh, "/n post blend reflesh./n");
 static unsigned int post_ctrl;
 module_param_named(post_ctrl, post_ctrl, uint, 0644);
-static bool vd1_en;
-module_param_named(vd1_en, vd1_en, bool, 0644);
 void di_post_switch_buffer(
 	struct DI_MIF_s		   *di_buf0_mif,
 	struct DI_MIF_s		   *di_buf1_mif,
@@ -2235,7 +2260,6 @@ void di_post_switch_buffer(
 
 	if (!is_meson_txlx_cpu())
 		invert_mv = 0;
-	DI_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG, vd1_en?1:0, 0, 1);
 	if (post_ctrl != 0)
 		DI_VSYNC_WR_MPEG_REG(DI_POST_CTRL, post_ctrl | (0x3 << 30));
 	else {
@@ -2259,14 +2283,12 @@ void di_post_switch_buffer(
 		(0x3 << 30)	/* post soft rst  post frame rst. */
 		);
 	}
-	if (di_ddr_en && mc_enable)
-		DI_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_CTRL, 1, 9, 1);
-	#if 0
+
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A) && di_ddr_en) {
 		DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0xc0200005);
 		DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x80200005);
-	}
-	#endif
+	} else if (di_ddr_en && mc_enable)
+		DI_VSYNC_WR_MPEG_REG_BITS(MCDI_MCVECRD_CTRL, 1, 9, 1);
 }
 
 static void set_post_mtnrd_mif(struct DI_SIM_MIF_s *mtnprd_mif,
@@ -2340,7 +2362,10 @@ void enable_di_post_2(
 		DI_VSYNC_WR_MPEG_REG(DI_DIWR_X,
 (di_diwr_mif->start_x << 16) | (di_diwr_mif->end_x));
 		DI_VSYNC_WR_MPEG_REG(DI_DIWR_Y, (3 << 30) |
-(di_diwr_mif->start_y << 16) | (di_diwr_mif->end_y));
+					(di_diwr_mif->start_y << 16) |
+						/* wr ext en from gxtvbb */
+							(1 << 15) |
+							(di_diwr_mif->end_y));
 		DI_VSYNC_WR_MPEG_REG(DI_DIWR_CTRL,
 			di_diwr_mif->canvas_num|
 			(urgent << 16) |
@@ -2350,12 +2375,7 @@ void enable_di_post_2(
 			di_buf1_mif->bit_mode,
 			di_buf2_mif->bit_mode,
 			di_diwr_mif->bit_mode);
-		pr_info("%s diwr mif<%u, %u; %u, %u>.\n",
-			__func__,
-			di_diwr_mif->start_x, di_diwr_mif->end_x,
-			di_diwr_mif->start_y, di_diwr_mif->end_y);
 	}
-
 	DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, 7, 22, 3);
 	DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
 		blend_en&0x1, 31, 1);
@@ -2389,12 +2409,10 @@ void enable_di_post_2(
 (0x3 << 30)
 /* post soft rst  post frame rst. */
 		);
-	#if 0
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A) && di_ddr_en) {
 		DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0xc0200005);
 		DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x80200005);
 	}
-	#endif
 }
 
 void disable_post_deinterlace_2(void)
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.h b/drivers/amlogic/media/deinterlace/deinterlace_hw.h
index af31d6f..53672d2 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.h
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.h
@@ -160,6 +160,7 @@ void di_post_gate_control(bool gate);
 void diwr_set_power_control(unsigned char enable);
 void di_hw_disable(bool mc_enable);
 void enable_di_pre_mif(bool enable, bool mc_enable);
+void reset_pre_simple_mif(void);
 void enable_di_post_mif(enum gate_mode_e mode);
 void di_hw_uninit(void);
 void combing_pd22_window_config(unsigned int width, unsigned int height);
diff --git a/drivers/amlogic/media/deinterlace/deinterlace_mtn.c b/drivers/amlogic/media/deinterlace/deinterlace_mtn.c
index 04cdda5..cc92763e 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_mtn.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_mtn.c
@@ -294,10 +294,6 @@ struct combing_status_s *adpative_combing_config(unsigned int width,
 
 void adpative_combing_exit(void)
 {
-	if (is_meson_gxtvbb_cpu() && dejaggy_enable) {
-		dejaggy_flag = -1;
-		DI_Wr_reg_bits(SRSHARP0_SHARP_DEJ1_MISC, 0, 3, 1);
-	}
 }
 static int cmb_adpset_cnt;
 unsigned int adp_set_level(unsigned int diff, unsigned int field_diff_num)
diff --git a/drivers/amlogic/media/deinterlace/di_pps.c b/drivers/amlogic/media/deinterlace/di_pps.c
index 501025a..2ba9160 100644
--- a/drivers/amlogic/media/deinterlace/di_pps.c
+++ b/drivers/amlogic/media/deinterlace/di_pps.c
@@ -17,6 +17,7 @@
 
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/amlogic/media/registers/regs/di_regs.h>
 #include <linux/amlogic/media/vfm/vframe.h>
 #include "di_pps.h"
 #include "register.h"
@@ -414,8 +415,11 @@ void di_pps_config(unsigned char path, int src_w, int src_h,
 		vsc_en = 1;
 	if (src_w != dst_w)
 		hsc_en = 1;
-	pr_info("[pps] input %d %d output %d %d.\n",
-		src_w, src_h, dst_w, dst_h);
+	pr_info("[pps] %s input %d %d output %d %d.\n",
+		path?"pre":"post", src_w, src_h, dst_w, dst_h);
+	/* config hdr size */
+	Wr_reg_bits(DI_HDR_IN_HSIZE, dst_w, 0, 13);
+	Wr_reg_bits(DI_HDR_IN_VSIZE, dst_h, 0, 13);
 	p_src_w = (prehsc_en ? ((src_w+1) >> 1) : src_w);
 	p_src_h = prevsc_en ? ((src_h+1) >> 1) : src_h;
 
@@ -521,7 +525,7 @@ void di_pps_config(unsigned char path, int src_w, int src_h,
 		(prevsc_en << 19) |      // prevsc_en
 		(vsc_en << 18)    |      // vsc_en
 		(hsc_en << 17)    |      // hsc_en
-		(1 << 16)         |      // sc_top_en
+		((vsc_en | hsc_en) << 16)         |      // sc_top_en
 		(1 << 15)         |      // vd1 sc out enable
 		(0 << 12)         |      // horz nonlinear 4region enable
 		(4 << 8)          |      // horz scaler bank length
diff --git a/drivers/amlogic/media/deinterlace/nr_downscale.c b/drivers/amlogic/media/deinterlace/nr_downscale.c
index adb0b28..dbc9811 100644
--- a/drivers/amlogic/media/deinterlace/nr_downscale.c
+++ b/drivers/amlogic/media/deinterlace/nr_downscale.c
@@ -44,13 +44,15 @@ static void nr_ds_hw_init(unsigned int width, unsigned int height)
 
 	RDMA_WR_BITS(VIUB_MISC_CTRL0, 3, 5, 2);   //Switch MIF to NR_DS
 	RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, width_out, 0, 8);  // config dsbuf_ocol
-	RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, height_out, 0, 8); // config dsbuf_orow
+	RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, height_out, 8, 8); // config dsbuf_orow
 
 	RDMA_WR_BITS(NRDSWR_X, (width_out-1), 0, 13);
 	RDMA_WR_BITS(NRDSWR_Y, (height_out-1), 0, 13);
 
 	RDMA_WR_BITS(NRDSWR_CAN_SIZE, (height_out-1), 0, 13);
 	RDMA_WR_BITS(NRDSWR_CAN_SIZE, (width_out-1), 16, 13);
+	/* little endian */
+	RDMA_WR_BITS(NRDSWR_CAN_SIZE, 1, 13, 1);
 
 	RDMA_WR_BITS(NR_DS_CTRL, v_step, 16, 6);
 	RDMA_WR_BITS(NR_DS_CTRL, h_step, 24, 6);
diff --git a/drivers/amlogic/media/deinterlace/nr_drv.c b/drivers/amlogic/media/deinterlace/nr_drv.c
index 19f7411..69bc081 100644
--- a/drivers/amlogic/media/deinterlace/nr_drv.c
+++ b/drivers/amlogic/media/deinterlace/nr_drv.c
@@ -1047,6 +1047,10 @@ static ssize_t nr_dbg_show(struct device *dev,
 
 	len += sprintf(buff+len,
 		"echo disable/enable to disable/enable nr(nr2/nr4/dnr).\n");
+	len += sprintf(buff+len,
+		"NR4_TOP_CTRL=0x%x DNR_CTRL=0x%x DI_NR_CTRL0=0x%x\n",
+		Rd(NR4_TOP_CTRL), Rd(DNR_CTRL), Rd(DI_NR_CTRL0));
+
 	return len;
 }
 
diff --git a/drivers/amlogic/media/deinterlace/register.h b/drivers/amlogic/media/deinterlace/register.h
index 3e1d5de..4b16385 100644
--- a/drivers/amlogic/media/deinterlace/register.h
+++ b/drivers/amlogic/media/deinterlace/register.h
@@ -18,6 +18,9 @@
 #ifndef __MACH_DEINTERLACE_REG_ADDR_H_
 #define __MACH_DEINTERLACE_REG_ADDR_H_
 #include <linux/amlogic/iomap.h>
+#include <linux/amlogic/media/registers/regs/di_regs.h>
+#include <linux/amlogic/media/registers/regs/viu_regs.h>
+#include <linux/amlogic/media/registers/regs/vdin_regs.h>
 
 #define Wr(adr, val) aml_write_vcbus(adr, val)
 #define Rd(adr) aml_read_vcbus(adr)
@@ -41,326 +44,7 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 #define HHI_VPU_CLKB_CNTL	0x83
 #define VPU_WRARB_REQEN_SLV_L1C1	((0x2795)) /* << 2) + 0xd0100000) */
 #define VPU_ARB_DBG_STAT_L1C1		((0x27b4)) /* << 2) + 0xd0100000) */
-#define SRSHARP0_SHARP_SR2_CTRL     ((0x3257)) /* << 2) + 0xd0100000) */
-/* Bit 24,  sr2_dejaggy_en  */
 
-#define SRSHARP0_SHARP_DEJ2_MISC    ((0x3263)) /* << 2) + 0xd0100000) */
-/*  Bit 3 sr2_dejaggy2_alpha_force,
- * force enable of the alpha for dejaggy2
- * Bit 2: 0	sr2_dejaggy2_alpha_value,
- * forced value of alpha for dejaggy2
- */
-
-#define SRSHARP0_DEJ_CTRL             0x3264  /*<< 2) + 0xd0100000)*/
-/* Bit 31:4    reserved
- * Bit 3:2,    reg_sr3_dejaggy_sameside_prtct
- * u2:  enable of sr3 dejaggy same side curve protect from filter,
- * [0] for proc, [1] for ctrl path,  default=3
- * Bit 1,      reg_sr3_dejaggy_sameside_mode
- * u1: mode of the sameside flag decision: default =1
- * Bit 0,      reg_sr3_dejaggy_enable
- * u1: enable of sr3 dejaggy: default =0
- */
-
-#define SRSHARP0_SHARP_DEJ2_PRC     ((0x3261)) /* << 2) + 0xd0100000) */
-/* Bit 31:24,  reg_dejaggy2_hcon_thrd             : .
- * unsigned, default =5,hcon threshold, only pixels with hcon equal or
- * larger than this value can be detected as jaggy2
- * Bit 23:16,  reg_dejaggy2_svdif_thrd            : . unsigned,
- * default =30,abs(sum(vdif[4])) threshold to decide jaggy2, only
- * pixels ws abs(sum(vdif[4]))>= thrd can be jaggy2
- * Bit 15: 8,  reg_dejaggy2_svdif_rate            : .
- * unsigned, default =32,sum(abs(vdif[4])) <= (rate*abs(sum(vdif[4]))/16)
- * rate to decide jaggy2,(normalized 2)
- * Bit  7: 6,  reserved
- * Bit  5: 0,  reg_dejaggy2_vdif_thrd             : .
- * signed, default =-3,vdif threshold for same trend decidion, these value
- * is the margin for not same trend; if >0, means need to be same trend, <0,
- * can be a little bit glitch
- */
-#define SRSHARP0_SHARP_DEJ1_PRC    ((0x3262)) /* << 2) + 0xd0100000) */
-/* Bit 31:24,  reg_dejaggy1_hcon_thrd             : . unsigned,
- * default =1,hcon threshold, only pixels with hcon equal or larger
- * than this value can be detected as jaggy1
- * Bit 23:16,  reg_dejaggy1_svdif_thrd            : . unsigned,
- * default =50,abs(sum(vdif[4])) threshold to decide jaggy1, only
- * pixels ws abs(sum(vdif[4]))<= thrd can be jaggy1
- * Bit 15: 8, reg_dejaggy1_svdif_rate            : . unsigned,
- * default =64,sum(abs(vdif[4])) <= (rate*abs(sum(vdif[4]))/16) rate
- * to decide jaggy2,(normalized 2)
- * Bit  7: 6,  reserved
- * Bit  5: 0,  reg_dejaggy1_dif12_rate            : . unsigned,
- * default =16,sum(abs(vdif2[3]))< (sum(abs(vdif[4]))*rate/32) rate
- * to decide jaggy2, (normalized 0.5)
- */
-#define SRSHARP0_SHARP_DEJ1_MISC   ((0x3264)) /* << 2) + 0xd0100000) */
-/* Bit 31:12,  reserved
- * Bit 11: 8,  reg_dejaggy1_svdif_ofst            : .
- * unsigned, default =2,sum(abs(vdif[4])) >= (rate*abs(sum(vdif[4]))/32 + ofst)
- * offset to decide jaggy2,(normalized 2)
- * Bit  7,     reg_dejaggy1_proc_chrm             : .
- * unsigned, default =1, enable to filter 2 pixels step on chroma
- * Bit  6,     reg_dejaggy1_proc_luma			  : .
- * unsigned, default =1, enable to filter 2 pixels step on luma
- * Bit  5: 4,  reg_dejaggy1_extend_mode           : .
- * unsigned, default =3, extend mode for dejaggy1 horizontally,
- * 0, no extnd, 1: exend 1 pixel, 2: extend 2 pixels, 3, extend 3 pixels
- * Bit  3,     reserved
- * Bit  2,     reg_dejaggy1_alpha_force           : .
- * unsigned, default =0, force enable of the alpha for dejaggy1
- * Bit  1: 0,  reg_dejaggy1_alpha_value           : .
- * unsigned, default =0, force value of the alpha for dejaggy1
- */
-
-
-
-/* vdin */
-#define VDIN_WR_CTRL					0x1220
-#define WR_CANVAS_BIT					0
-#define WR_CANVAS_WID					8
-/* 0xd0104880 */
-/* Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2.
- *		0: Output every even pixels' CbCr;
- *		1: Output every odd pixels' CbCr;
- *		2: Output an average value per even&odd pair of pixels;
- *		3: Output all CbCr.
- * (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.)
- * Bit 29 no_clk_gate: disable vid_wr_mif clock gating function.
- * Bit 28 clear write response counter in the vdin write memory interface
- * Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line
- * end indication in the vdin write memory interface
- * Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1.
- * Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1.
- * Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1.
- * Bit 23 vdin frame reset enble, if true, it will provide frame reset during
- * go_field(vsync) to the modules after that
- * Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will
- * reset during go_field (vsync)
- * Bit 21 vdin direct write done status clear bi
- * Bit 20 vdin NR write done status clear bit
- * Bit 18 swap_cbcr. Applicable only to bit[13:12]=2.
- *		0: Output CbCr (NV12);
- *		1: Output CrCb (NV21).
- * Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even
- * lines' CbCr;
- *		1: Output every odd lines' CbCr;
- *		2: Reserved;
- *		3: Output all CbCr.
- * Bit 13:12 vdin write format,
- *		0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas,
- *		2: Y to luma canvas, CbCr to chroma canvas.
- * For NV12/21, also define Bit
- * 31:30, 17:16, and bit 18.
- * Bit 11 vdin write canvas double buffer enable, means the canvas address will
- * be latched by vsync before using
- * Bit 10 1: disable ctrl_reg write pulse which will reset internal counter.
- * when bit 11 is 1, this bit should be 1.
- * Bit 9 vdin write request urgent
- * Bit 8 vdin write request enable
- * Bit 7:0 Write luma canvas address
- */
-/* timerc */
-/* vd1 */
-#define VD1_IF0_GEN_REG					0x1a50
-
-#define VD1_IF0_CANVAS0					0x1a51
-		/* 0xd0106944 */
-#define VD1_IF0_CANVAS1					0x1a52
-		/* 0xd0106948 */
-#define VD1_IF0_LUMA_X0					0x1a53
-		/* 0xd010694c */
-#define VD1_IF0_LUMA_Y0					0x1a54
-		/* 0xd0106950 */
-#define VD1_IF0_CHROMA_X0				0x1a55
-		/* 0xd0106954 */
-#define VD1_IF0_CHROMA_Y0				0x1a56
-		/* 0xd0106958 */
-#define VD1_IF0_LUMA_X1					0x1a57
-
-#define VD1_IF0_LUMA_Y1					0x1a58
-
-#define VD1_IF0_CHROMA_X1				0x1a59
-
-#define VD1_IF0_CHROMA_Y1				0x1a5a
-
-#define VD1_IF0_RPT_LOOP				0x1a5b
-
-#define VD1_IF0_LUMA0_RPT_PAT				0x1a5c
-
-#define VD1_IF0_CHROMA0_RPT_PAT				0x1a5d
-
-#define VD1_IF0_LUMA1_RPT_PAT				0x1a5e
-
-#define VD1_IF0_CHROMA1_RPT_PAT				0x1a5f
-
-#define VD1_IF0_LUMA_PSEL				0x1a60
-
-#define VD1_IF0_CHROMA_PSEL				0x1a61
-
-#define VD1_IF0_DUMMY_PIXEL				0x1a62
-
-#define VD1_IF0_LUMA_FIFO_SIZE				0x1a63
-
-#define VD1_IF0_RANGE_MAP_Y				0x1a6a
-
-#define VD1_IF0_RANGE_MAP_CB				0x1a6b
-
-#define VD1_IF0_RANGE_MAP_CR				0x1a6c
-
-#define VD1_IF0_GEN_REG2				0x1a6d
-
-#define VD1_IF0_PROT_CNTL				0x1a6e
-
-#define VIU_VD1_FMT_CTRL				0x1a68
-
-#define VIU_VD1_FMT_W					0x1a69
-
-#define VD1_IF0_LUMA_FIFO_SIZE				0x1a63
-		/* 0xd010698c */
-#define VD2_IF0_LUMA_FIFO_SIZE				0x1a83
-		/* 0xd0106a0c */
-		/* 0xd0106974 */
-#define VIU_OSD1_CTRL_STAT				0x1a10
-		/* 0xd0106840 */
-/* afbc */
-#define AFBC_ENABLE                        ((0x1ae0)) /* << 2) + 0xd0100000) */
-/* Bit   31:1,     reserved
- * Bit   8,        dec_enable        unsigned  , default = 0
- * Bit   7:1,      reserved
- * Bit   0,        frm_start         unsigned  , default = 0
- */
-#define AFBC_MODE                          ((0x1ae1)) /* << 2) + 0xd0100000) */
-/* Bit   31,       soft_reset        the use as go_field
- * Bit   30:28,    reserved
- * Bit   27:26,    rev_mode          uns, default = 0 , reverse mode
- * Bit   25:24,    mif_urgent        uns, default = 3 ,
- * info mif and data mif urgent
- * Bit   22:16,    hold_line_num
- * Bit   15:14,    burst_len         uns, default = 1,
- *		0: burst1 1:burst2 2:burst4
- * Bit   13:8,     compbits_yuv      uns, default = 0 ,
- *		bit 1:0,: y  component bitwidth : 00-8bit 01-9bit 10-10bit
- *		bit 3:2,: u  component bitwidth : 00-8bit 01-9bit 10-10bit
- *		bit 5:4,: v  component bitwidth : 00-8bit 01-9bit 10-10bit
- * Bit   7:6,      vert_skip_y       uns, default = 0 ,
- * luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
- * Bit   5:4,      horz_skip_y       uns, default = 0 ,
- * luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
- * Bit   3:2,      vert_skip_uv      uns, default = 0 ,
- * chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
- * Bit   1:0,      horz_skip_uv      uns, default = 0 ,
- * chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
- */
-#define AFBC_SIZE_IN                       ((0x1ae2)) /* << 2) + 0xd0100000) */
-/* Bit   31:29,    reserved
- * Bit   28:16     hsize_in          uns, default = 1920 ,
- * pic horz size in  unit: pixel
- * Bit   15:13,    reserved
- * Bit   12:0,     vsize_in          uns, default = 1080 ,
- * pic vert size in  unit: pixel
- */
-#define AFBC_DEC_DEF_COLOR                 ((0x1ae3)) /* << 2) + 0xd0100000) */
-/* Bit   31:29,    reserved
- * Bit   29:20,   def_color_y        uns, default = 0,
- * afbc dec y default setting value
- * Bit   19:10,   def_color_u        uns, default = 0,
- * afbc dec u default setting value
- * Bit    9: 0,   def_color_v        uns, default = 0,
- * afbc dec v default setting value
- */
-#define AFBC_CONV_CTRL                     ((0x1ae4)) /* << 2) + 0xd0100000) */
-/* Bit   31:12,   reserved
- * Bit   11: 0,   conv_lbuf_len       uns, default = 256,
- * unit=16 pixel need to set = 2^n
- */
-#define AFBC_LBUF_DEPTH                    ((0x1ae5)) /* << 2) + 0xd0100000) */
-/* Bit   31:28,   reserved
- * Bit   27:16,   dec_lbuf_depth      uns, default = 128; // unit= 8 pixel
- * Bit   15:12,   reserved
- * Bit   11:0,    mif_lbuf_depth      uns, default = 128;
- */
-#define AFBC_HEAD_BADDR                    ((0x1ae6)) /* << 2) + 0xd0100000) */
-/* Bit   31:0,   mif_info_baddr      uns, default = 32'h0; */
-#define AFBC_BODY_BADDR                    ((0x1ae7)) /* << 2) + 0xd0100000) */
-/* Bit   31:0,   mif_data_baddr      uns, default = 32'h0001_0000; */
-#define AFBC_SIZE_OUT                    ((0x1ae8)) /* << 2) + 0xd0100000) */
-/* Bit   31:29,   reserved
- * Bit   28:16,   hsize_out    uns, default = 1920    ;    unit: 1 pixel
- * Bit   15:13,   reserved
- * Bit    12:0,   vsize_out    uns, default = 1080 ;       unit: 1 pixel
- */
-#define AFBC_OUT_YSCOPE                    ((0x1ae9)) /* << 2) + 0xd0100000) */
-/* Bit   31:29,   reserved
- * Bit   28:16,   out_vert_bgn        uns, default = 0    ; // unit: 1 pixel
- * Bit   15:13,   reserved
- * Bit    12:0,   out_vert_end        uns, default = 1079 ; // unit: 1 pixel
- */
-#define AFBC_STAT                          ((0x1aea)) /* << 2) + 0xd0100000) */
-/* Bit   31:1,   reserved
- * Bit      0,   frm_end_stat         uns, frame end status
- */
-#define AFBC_VD_CFMT_CTRL                  ((0x1aeb)) /* << 2) + 0xd0100000) */
-/* Bit 31    it true, disable clock, otherwise enable clock
- * Bit 30    soft rst bit
- * Bit 28    if true, horizontal formatter use repeating to generete pixel,
- * otherwise use bilinear interpolation
- * Bit 27:24 horizontal formatter initial phase
- * Bit 23    horizontal formatter repeat pixel 0 enable
- * Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
- * Bit 20    horizontal formatter enable
- * Bit 19    if true, always use phase0 while vertical formater,
- * meaning always
- * repeat data, no interpolation
- * Bit 18    if true, disable vertical formatter chroma repeat last line
- * Bit 17    veritcal formatter dont need repeat line on phase0,
- *		1: enable, 0: disable
- * Bit 16    veritcal formatter repeat line 0 enable
- * Bit 15:12 vertical formatter skip line num at the beginning
- * Bit 11:8  vertical formatter initial phase
- * Bit 7:1   vertical formatter phase step (3.4)
- * Bit 0     vertical formatter enable
- */
-#define AFBC_VD_CFMT_W                     ((0x1aec)) /* << 2) + 0xd0100000) */
-/* Bit 27:16  horizontal formatter width */
-/* Bit 11:0   vertical formatter width */
-#define AFBC_MIF_HOR_SCOPE                 ((0x1aed)) /* << 2) + 0xd0100000) */
-/* Bit   31:26,   reserved
- * Bit   25:16,   mif_blk_bgn_h        uns, default = 0  ;
- *		// unit: 32 pixel/block hor
- * Bit   15:10,   reserved
- * Bit    9: 0,   mif_blk_end_h        uns, default = 59 ;
- *		// unit: 32 pixel/block hor
- */
-#define AFBC_MIF_VER_SCOPE                 ((0x1aee)) /* << 2) + 0xd0100000) */
-/* Bit   31:28,   reserved
- * Bit   27:16,   mif_blk_bgn_v        uns, default = 0  ;
- *		// unit: 32 pixel/block ver
- * Bit   15:12,   reserved
- * Bit   11: 0,   mif_blk_end_v        uns, default = 269;
- *		// unit: 32 pixel/block ver
- */
-#define AFBC_PIXEL_HOR_SCOPE               ((0x1aef)) /* << 2) + 0xd0100000) */
-/* Bit   31:29,   reserved
- * Bit   28:16,   dec_pixel_bgn_h        uns, default = 0  ;
- *		// unit: pixel
- * Bit   15:13,   reserved
- * Bit   12: 0,   dec_pixel_end_h        uns, default = 1919 ; // unit: pixel
- */
-#define AFBC_PIXEL_VER_SCOPE               ((0x1af0)) /* << 2) + 0xd0100000) */
-/* Bit   31:29,   reserved
- * Bit   28:16,   dec_pixel_bgn_v        uns, default = 0  ; // unit: pixel
- * Bit   15:13,   reserved
- * Bit   12: 0,   dec_pixel_end_v        uns, default = 1079 ; // unit: pixel
- */
-#define AFBC_VD_CFMT_H                     ((0x1af1)) /* << 2) + 0xd0100000) */
-/* Bit 12:0   vertical formatter height */
-
-
-/* viu mux */
-#define VIU_MISC_CTRL0					0x1a06
-		/* 0xd0106818 */
-#define VIU_MISC_CTRL1					0x1a07
-#define VD1_AFBCD0_MISC_CTRL			0x1a0a
 #define VIUB_SW_RESET					0x2001
 #define VIUB_SW_RESET0					0x2002
 #define VIUB_MISC_CTRL0					0x2006
@@ -369,6 +53,7 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 #define VIUB_GCLK_CTRL1					0x2008
 #define VIUB_GCLK_CTRL2					0x2009
 #define VIUB_GCLK_CTRL3					0x200a
+/* txl add if2 */
 #define DI_IF2_GEN_REG					0x2010
 #define DI_IF2_CANVAS0					0x2011
 #define DI_IF2_LUMA_X0					0x2012
@@ -519,69 +204,6 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 #define DI_HSC_INI_PAT_CTRL				0x376b
 #define DI_SC_GCLK_CTRL					0x376c
 #define DI_SC_HOLD_LINE					0x376d
-/* DI HDR */
-#define DI_HDR_IN_HSIZE					0x376e
-#define DI_HDR_IN_VSIZE					0x376f
-#define DI_HDR2_CTRL					0x3800
-#define DI_HDR2_CLK_GATE				0x3881
-#define DI_HDR2_MATRIXI_COEF00_01		0x3882
-#define DI_HDR2_MATRIXI_COEF02_10		0x3883
-#define DI_HDR2_MATRIXI_COEF11_12		0x3884
-#define DI_HDR2_MATRIXI_COEF20_21		0x3885
-#define DI_HDR2_MATRIXI_COEF22			0x3886
-#define DI_HDR2_MATRIXI_COEF30_31		0x3887
-#define DI_HDR2_MATRIXI_COEF32_40		0x3888
-#define DI_HDR2_MATRIXI_COEF41_42		0x3889
-#define DI_HDR2_MATRIXI_OFFSET0_1		0x388A
-#define DI_HDR2_MATRIXI_OFFSET2			0x388B
-#define DI_HDR2_MATRIXI_PRE_OFFSET0_1	0x388C
-#define DI_HDR2_MATRIXI_PRE_OFFSET2		0x388D
-#define DI_HDR2_MATRIXO_COEF00_01		0x388E
-#define DI_HDR2_MATRIXO_COEF02_10		0x388F
-#define DI_HDR2_MATRIXO_COEF11_12		0x3890
-#define DI_HDR2_MATRIXO_COEF20_21		0x3891
-#define DI_HDR2_MATRIXO_COEF22			0x3892
-#define DI_HDR2_MATRIXO_COEF30_31		0x3893
-#define DI_HDR2_MATRIXO_COEF32_40		0x3894
-#define DI_HDR2_MATRIXO_COEF41_42		0x3895
-#define DI_HDR2_MATRIXO_OFFSET0_1		0x3896
-#define DI_HDR2_MATRIXO_OFFSET2			0x3897
-#define DI_HDR2_MATRIXO_PRE_OFFSET0_1	0x3898
-#define DI_HDR2_MATRIXO_PRE_OFFSET2		0x3899
-#define DI_HDR2_MATRIXI_CLIP			0x389A
-#define DI_HDR2_MATRIXO_CLIP			0x389B
-#define DI_HDR2_CGAIN_OFFT				0x389C
-#define DI_EOTF_LUT_ADDR_PORT			0x389E
-#define DI_EOTF_LUT_DATA_PORT			0x389F
-#define DI_OETF_LUT_ADDR_PORT			0x38A0
-#define DI_OETF_LUT_DATA_PORT			0x38A1
-#define DI_CGAIN_LUT_ADDR_PORT			0x38A2
-#define DI_CGAIN_LUT_DATA_PORT			0x38A3
-#define DI_HDR2_CGAIN_COEF0				0x38A4
-#define DI_HDR2_CGAIN_COEF1				0x38A5
-#define DI_OGAIN_LUT_ADDR_PORT			0x38A6
-#define DI_OGAIN_LUT_DATA_PORT			0x38A7
-#define DI_HDR2_ADPS_CTRL				0x38A8
-#define DI_HDR2_ADPS_ALPHA0				0x38A9
-#define DI_HDR2_ADPS_ALPHA1				0x38AA
-#define DI_HDR2_ADPS_BETA0				0x38AB
-#define DI_HDR2_ADPS_BETA1				0x38AC
-#define DI_HDR2_ADPS_BETA2				0x38AD
-#define DI_HDR2_ADPS_COEF0				0x38AE
-#define DI_HDR2_ADPS_COEF1				0x38AF
-#define DI_HDR2_GMUT_CTRL				0x38B0
-#define DI_HDR2_GMUT_COEF0				0x38B1
-#define DI_HDR2_GMUT_COEF1				0x38B2
-#define DI_HDR2_GMUT_COEF2				0x38B3
-#define DI_HDR2_GMUT_COEF3				0x38B4
-#define DI_HDR2_GMUT_COEF4				0x38B5
-#define DI_HDR2_PIPE_CTRL1				0x38B6
-#define DI_HDR2_PIPE_CTRL2				0x38B7
-#define DI_HDR2_PIPE_CTRL3				0x38B8
-#define DI_HDR2_PROC_WIN1				0x38B9
-#define DI_HDR2_PROC_WIN2				0x38BA
-#define DI_HDR2_MATRIXI_EN_CTRL			0x38BB
-#define DI_HDR2_MATRIXO_EN_CTRL			0x38BC
 /* NR DOWNSAMPLE */
 #define NRDSWR_X						0x37f9
 #define NRDSWR_Y						0x37fa
@@ -591,7 +213,6 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 #define NR_DS_CTRL						0x3741
 #define NR_DS_OFFSET					0x3742
 #define NR_DS_BLD_COEF					0x3743
-
 /* di */
 #define DI_IF1_URGENT_CTRL                  (0x20a3)  /*  << 2 + 0xd0100000*/
 /* bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 ,
@@ -638,7 +259,7 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 /* bit  2,      check322p_en */
 /* bit  1,      mtn_en */
 /* bit  0,      nr_en */
-#define DI_POST_CTRL                      ((0x1701)) /* << 2) + 0xd0100000) */
+/* #define DI_POST_CTRL                      ((0x1701)) */
 /* bit 31,      cbus_post_frame_rst */
 /* bit 30,      cbus_post_soft_rst */
 /* bit 29,      post_field_num */
@@ -657,7 +278,7 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 /* bit  2,      di_ei_en */
 /* bit  1,      di_buf1_en */
 /* bit  0,      di_buf0_en */
-#define DI_POST_SIZE                      ((0x1702)) /* << 2) + 0xd0100000) */
+/* #define DI_POST_SIZE                      ((0x1702)) */
 /* bit 28:16,    vsize1post */
 /* bit 12:0,     hsize1post */
 #define DI_PRE_SIZE                       ((0x1703)) /* << 2) + 0xd0100000) */
@@ -1984,7 +1605,7 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 #define DI_MEM_GEN_REG2                  ((0x1792)) /* << 2) + 0xd0100000) */
 #define DI_MEM_FMT_CTRL                  ((0x17e6)) /* << 2) + 0xd0100000) */
 #define DI_MEM_FMT_W                     ((0x17e7)) /* << 2) + 0xd0100000) */
-#define DI_IF1_GEN_REG                   ((0x17e8)) /* << 2) + 0xd0100000) */
+/* #define DI_IF1_GEN_REG                   ((0x17e8)) + 0xd0100000) */
 #define DI_IF1_CANVAS0                   ((0x17e9)) /* << 2) + 0xd0100000) */
 #define DI_IF1_LUMA_X0                   ((0x17ea)) /* << 2) + 0xd0100000) */
 #define DI_IF1_LUMA_Y0                   ((0x17eb)) /* << 2) + 0xd0100000) */
@@ -2048,21 +1669,13 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
 /* Bit 7:1   vertical formatter phase step (3.4) */
 /* Bit 0     vertical formatter enable */
 #define VIU_VD1_FMT_W				    0x1a69
-/*g12a addr change to 0x3219*/
 /* ((0x1a69  << 2) + 0xd0100000) */
 /* Bit 27:16  horizontal formatter width */
 /* Bit 11:0   vertical formatter width */
 
 
 #define VD1_IF0_GEN_REG2		0x1a6d
-#define VD2_IF0_GEN_REG2		0x1a8d
 
-#define VD1_IF0_GEN_REG3                0x1aa7
-		/* 0xd0106a9c */
-/*bit9:8	bit mode: 0 = 8bits, 1=10bits 422,  2 = 10bits 444 */
-#define DI_IF1_GEN_REG3                 0x20a7
-		/* 0xd010829c */
-/*bit9:8	bit mode: 0 = 8bits, 1=10bits 422,  2 = 10bits 444 */
 #define DI_INP_GEN_REG3                 0x20a8
 		/* 0xd01082a0 */
 /*bit9:8	bit mode: 0 = 8bits, 1=10bits 422,  2 = 10bits 444 */
diff --git a/include/linux/amlogic/media/registers/regs/di_regs.h b/include/linux/amlogic/media/registers/regs/di_regs.h
index ebef0a5..c53d545 100644
--- a/include/linux/amlogic/media/registers/regs/di_regs.h
+++ b/include/linux/amlogic/media/registers/regs/di_regs.h
@@ -18,103 +18,78 @@
 #ifndef DI_REGS_HEADER_
 #define DI_REGS_HEADER_
 
-#define DI_POST_CTRL 0x1701
-#define DI_POST_SIZE 0x1702
-#define DI_CONTWR_X 0x17a0
-#define DI_CONTWR_Y 0x17a1
-#define DI_CONTWR_CTRL 0x17a2
-#define DI_CONTPRD_X 0x17a3
-#define DI_CONTPRD_Y 0x17a4
-#define DI_CONTP2RD_X 0x17a5
-#define DI_CONTP2RD_Y 0x17a6
-#define DI_CONTRD_CTRL 0x17a7
-#define DI_NRWR_X 0x17c0
-#define DI_NRWR_Y 0x17c1
-#define DI_NRWR_CTRL 0x17c2
-#define DI_MTNWR_X 0x17c3
-#define DI_MTNWR_Y 0x17c4
-#define DI_MTNWR_CTRL 0x17c5
-#define DI_DIWR_X 0x17c6
-#define DI_DIWR_Y 0x17c7
-#define DI_DIWR_CTRL 0x17c8
-#define DI_MTNCRD_X 0x17c9
-#define DI_MTNCRD_Y 0x17ca
-#define DI_MTNPRD_X 0x17cb
-#define DI_MTNPRD_Y 0x17cc
-#define DI_MTNRD_CTRL 0x17cd
-#define DI_INP_GEN_REG 0x17ce
-#define DI_INP_CANVAS0 0x17cf
-#define DI_INP_LUMA_X0 0x17d0
-#define DI_INP_LUMA_Y0 0x17d1
-#define DI_INP_CHROMA_X0 0x17d2
-#define DI_INP_CHROMA_Y0 0x17d3
-#define DI_INP_RPT_LOOP 0x17d4
-#define DI_INP_LUMA0_RPT_PAT 0x17d5
-#define DI_INP_CHROMA0_RPT_PAT 0x17d6
-#define DI_INP_DUMMY_PIXEL 0x17d7
-#define DI_INP_LUMA_FIFO_SIZE 0x17d8
-#define DI_INP_RANGE_MAP_Y 0x17ba
-#define DI_INP_RANGE_MAP_CB 0x17bb
-#define DI_INP_RANGE_MAP_CR 0x17bc
-#define DI_INP_GEN_REG2 0x1791
-#define DI_INP_FMT_CTRL 0x17d9
-#define DI_INP_FMT_W 0x17da
-#define DI_MEM_GEN_REG 0x17db
-#define DI_MEM_CANVAS0 0x17dc
-#define DI_MEM_LUMA_X0 0x17dd
-#define DI_MEM_LUMA_Y0 0x17de
-#define DI_MEM_CHROMA_X0 0x17df
-#define DI_MEM_CHROMA_Y0 0x17e0
-#define DI_MEM_RPT_LOOP 0x17e1
-#define DI_MEM_LUMA0_RPT_PAT 0x17e2
-#define DI_MEM_CHROMA0_RPT_PAT 0x17e3
-#define DI_MEM_DUMMY_PIXEL 0x17e4
-#define DI_MEM_LUMA_FIFO_SIZE 0x17e5
-#define DI_MEM_RANGE_MAP_Y 0x17bd
-#define DI_MEM_RANGE_MAP_CB 0x17be
-#define DI_MEM_RANGE_MAP_CR 0x17bf
-#define DI_MEM_GEN_REG2 0x1792
-#define DI_MEM_FMT_CTRL 0x17e6
-#define DI_MEM_FMT_W 0x17e7
-#define DI_IF1_GEN_REG 0x17e8
-#define DI_IF1_CANVAS0 0x17e9
-#define DI_IF1_LUMA_X0 0x17ea
-#define DI_IF1_LUMA_Y0 0x17eb
-#define DI_IF1_CHROMA_X0 0x17ec
-#define DI_IF1_CHROMA_Y0 0x17ed
-#define DI_IF1_RPT_LOOP 0x17ee
-#define DI_IF1_LUMA0_RPT_PAT 0x17ef
-#define DI_IF1_CHROMA0_RPT_PAT 0x17f0
-#define DI_IF1_DUMMY_PIXEL 0x17f1
-#define DI_IF1_LUMA_FIFO_SIZE 0x17f2
-#define DI_IF1_RANGE_MAP_Y 0x17fc
-#define DI_IF1_RANGE_MAP_CB 0x17fd
-#define DI_IF1_RANGE_MAP_CR 0x17fe
-#define DI_IF1_GEN_REG2 0x1790
-#define DI_IF1_FMT_CTRL 0x17f3
-#define DI_IF1_FMT_W 0x17f4
-#define DI_CHAN2_GEN_REG 0x17f5
-#define DI_CHAN2_CANVAS0 0x17f6
-#define DI_CHAN2_LUMA_X0 0x17f7
-#define DI_CHAN2_LUMA_Y0 0x17f8
-#define DI_CHAN2_CHROMA_X0 0x17f9
-#define DI_CHAN2_CHROMA_Y0 0x17fa
-#define DI_CHAN2_RPT_LOOP 0x17fb
-#define DI_CHAN2_LUMA0_RPT_PAT 0x17b0
-#define DI_CHAN2_CHROMA0_RPT_PAT 0x17b1
-#define DI_CHAN2_DUMMY_PIXEL 0x17b2
-#define DI_CHAN2_LUMA_FIFO_SIZE 0x17b3
-#define DI_CHAN2_RANGE_MAP_Y 0x17b4
-#define DI_CHAN2_RANGE_MAP_CB 0x17b5
-#define DI_CHAN2_RANGE_MAP_CR 0x17b6
-#define DI_CHAN2_GEN_REG2 0x17b7
-#define DI_CHAN2_FMT_CTRL 0x17b8
-#define DI_CHAN2_FMT_W 0x17b9
-
-#define VD1_IF0_GEN_REG3 0x1aa7
-#define DI_IF1_GEN_REG3  0x20a7
-#define DI_IF2_GEN_REG3  0x2022
-#define DI_IF0_GEN_REG3  0x2042
+#define DI_POST_CTRL	0x1701
+#define DI_POST_SIZE	0x1702
+#define DI_IF1_GEN_REG	0x17e8
+#define VD1_IF0_GEN_REG2	0x1a6d
+#define VD2_IF0_GEN_REG2	0x1a8d
+#define VD1_IF0_GEN_REG3	0x1aa7
+#define DI_IF1_GEN_REG3	0x20a7
+#define DI_IF2_GEN_REG3	0x2022
+#define DI_IF0_GEN_REG3	0x2042
+/* DI HDR */
+#define DI_HDR_IN_HSIZE	0x376e
+#define DI_HDR_IN_VSIZE	0x376f
+#define DI_HDR2_CTRL	0x3800
+#define DI_HDR2_CLK_GATE	0x3881
+#define DI_HDR2_MATRIXI_COEF00_01	0x3882
+#define DI_HDR2_MATRIXI_COEF02_10	0x3883
+#define DI_HDR2_MATRIXI_COEF11_12	0x3884
+#define DI_HDR2_MATRIXI_COEF20_21	0x3885
+#define DI_HDR2_MATRIXI_COEF22	0x3886
+#define DI_HDR2_MATRIXI_COEF30_31	0x3887
+#define DI_HDR2_MATRIXI_COEF32_40	0x3888
+#define DI_HDR2_MATRIXI_COEF41_42	0x3889
+#define DI_HDR2_MATRIXI_OFFSET0_1	0x388A
+#define DI_HDR2_MATRIXI_OFFSET2	0x388B
+#define DI_HDR2_MATRIXI_PRE_OFFSET0_1	0x388C
+#define DI_HDR2_MATRIXI_PRE_OFFSET2	0x388D
+#define DI_HDR2_MATRIXO_COEF00_01	0x388E
+#define DI_HDR2_MATRIXO_COEF02_10	0x388F
+#define DI_HDR2_MATRIXO_COEF11_12	0x3890
+#define DI_HDR2_MATRIXO_COEF20_21	0x3891
+#define DI_HDR2_MATRIXO_COEF22	0x3892
+#define DI_HDR2_MATRIXO_COEF30_31	0x3893
+#define DI_HDR2_MATRIXO_COEF32_40	0x3894
+#define DI_HDR2_MATRIXO_COEF41_42	0x3895
+#define DI_HDR2_MATRIXO_OFFSET0_1	0x3896
+#define DI_HDR2_MATRIXO_OFFSET2	0x3897
+#define DI_HDR2_MATRIXO_PRE_OFFSET0_1	0x3898
+#define DI_HDR2_MATRIXO_PRE_OFFSET2	0x3899
+#define DI_HDR2_MATRIXI_CLIP	0x389A
+#define DI_HDR2_MATRIXO_CLIP	0x389B
+#define DI_HDR2_CGAIN_OFFT	0x389C
+#define DI_EOTF_LUT_ADDR_PORT	0x389E
+#define DI_EOTF_LUT_DATA_PORT	0x389F
+#define DI_OETF_LUT_ADDR_PORT	0x38A0
+#define DI_OETF_LUT_DATA_PORT	0x38A1
+#define DI_CGAIN_LUT_ADDR_PORT	0x38A2
+#define DI_CGAIN_LUT_DATA_PORT	0x38A3
+#define DI_HDR2_CGAIN_COEF0	0x38A4
+#define DI_HDR2_CGAIN_COEF1	0x38A5
+#define DI_OGAIN_LUT_ADDR_PORT	0x38A6
+#define DI_OGAIN_LUT_DATA_PORT	0x38A7
+#define DI_HDR2_ADPS_CTRL	0x38A8
+#define DI_HDR2_ADPS_ALPHA0	0x38A9
+#define DI_HDR2_ADPS_ALPHA1	0x38AA
+#define DI_HDR2_ADPS_BETA0	0x38AB
+#define DI_HDR2_ADPS_BETA1	0x38AC
+#define DI_HDR2_ADPS_BETA2	0x38AD
+#define DI_HDR2_ADPS_COEF0	0x38AE
+#define DI_HDR2_ADPS_COEF1	0x38AF
+#define DI_HDR2_GMUT_CTRL	0x38B0
+#define DI_HDR2_GMUT_COEF0	0x38B1
+#define DI_HDR2_GMUT_COEF1	0x38B2
+#define DI_HDR2_GMUT_COEF2	0x38B3
+#define DI_HDR2_GMUT_COEF3	0x38B4
+#define DI_HDR2_GMUT_COEF4	0x38B5
+#define DI_HDR2_PIPE_CTRL1	0x38B6
+#define DI_HDR2_PIPE_CTRL2	0x38B7
+#define DI_HDR2_PIPE_CTRL3	0x38B8
+#define DI_HDR2_PROC_WIN1	0x38B9
+#define DI_HDR2_PROC_WIN2	0x38BA
+#define DI_HDR2_MATRIXI_EN_CTRL	0x38BB
+#define DI_HDR2_MATRIXO_EN_CTRL	0x38BC
 #endif