From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 09:55:12 +0000 (+0100) Subject: arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain X-Git-Tag: v6.6.7~3035^2~4^2~37 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=61348fe9e75b7edb25b26ce789a9aec617b20090;p=platform%2Fkernel%2Flinux-starfive.git arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain The mfg_ref_sel clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-9-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 34631ad..a29cdff 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -499,8 +499,9 @@ power-domain@MT8192_POWER_DOMAIN_MFG0 { reg = ; - clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; - clock-names = "mfg"; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, + <&topckgen CLK_TOP_MFG_REF_SEL>; + clock-names = "mfg", "alt"; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>;