From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 20 Nov 2022 12:22:11 +0000 (+0000)
Subject: [X86] Remove unnecessary bit test instruction overrides from znver2 model
X-Git-Tag: upstream/17.0.6~27075
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=611db1c78fcbbe5de633101006dc5c4c087b72cb;p=platform%2Fupstream%2Fllvm.git

[X86] Remove unnecessary bit test instruction overrides from znver2 model

Reported by D138359 and confirmed with AMD SoG - matches znver1 model
---

diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index 0428656..90b66d2 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -706,18 +706,7 @@ def Zn2WriteALULat2Ld : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
   let Latency = 6;
 }
 
-// BT.
-// m,i.
-def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
-
 // BTR BTS BTC.
-// r,r,i.
-def Zn2WriteBTRSC : SchedWriteRes<[Zn2ALU]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-}
-def : InstRW<[Zn2WriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
-
 // m,r,i.
 def Zn2WriteBTRSCm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
   let Latency = 6;