From: Thomas Symalla <thomas.symalla@amd.com>
Date: Tue, 9 May 2023 15:24:00 +0000 (+0200)
Subject: [NFC][AMDGPU] Add option to test.
X-Git-Tag: upstream/17.0.6~9006
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=60a4cb707658b6b99d9263cae9957a4c64ad96d3;p=platform%2Fupstream%2Fllvm.git

[NFC][AMDGPU] Add option to test.
---

diff --git a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
index 6171d9c..cd3cbb4 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -start-before=amdgpu-late-codegenprepare < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -disable-machine-sink=1 -start-before=amdgpu-late-codegenprepare < %s | FileCheck -check-prefix=GFX10 %s
 
 define float @fold_abs_in_branch(float %arg1, float %arg2) {
 ; GFX10-LABEL: fold_abs_in_branch:
@@ -10,10 +10,10 @@ define float @fold_abs_in_branch(float %arg1, float %arg2) {
 ; GFX10-NEXT:    s_mov_b32 s4, exec_lo
 ; GFX10-NEXT:    v_add_f32_e32 v1, v0, v1
 ; GFX10-NEXT:    v_add_f32_e64 v0, |v1|, |v1|
+; GFX10-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v1
 ; GFX10-NEXT:    v_cmpx_nlt_f32_e32 1.0, v0
 ; GFX10-NEXT:  ; %bb.1: ; %if
-; GFX10-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v1
-; GFX10-NEXT:    v_mul_f32_e32 v0, 0x3e4ccccd, v0
+; GFX10-NEXT:    v_mul_f32_e32 v0, 0x3e4ccccd, v1
 ; GFX10-NEXT:  ; %bb.2: ; %exit
 ; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
@@ -40,10 +40,10 @@ define float @fold_abs_in_branch_undef(float %arg1, float %arg2) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_add_f32_e64 v0, |s4|, |s4|
+; GFX10-NEXT:    s_bitset0_b32 s4, 31
 ; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 1.0, v0
 ; GFX10-NEXT:    s_cbranch_vccnz .LBB1_2
 ; GFX10-NEXT:  ; %bb.1: ; %if
-; GFX10-NEXT:    s_bitset0_b32 s4, 31
 ; GFX10-NEXT:    v_mul_f32_e64 v0, 0x3e4ccccd, s4
 ; GFX10-NEXT:  .LBB1_2: ; %exit
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
@@ -70,10 +70,10 @@ define float @fold_abs_in_branch_poison(float %arg1, float %arg2) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_add_f32_e64 v0, |s4|, |s4|
+; GFX10-NEXT:    s_bitset0_b32 s4, 31
 ; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 1.0, v0
 ; GFX10-NEXT:    s_cbranch_vccnz .LBB2_2
 ; GFX10-NEXT:  ; %bb.1: ; %if
-; GFX10-NEXT:    s_bitset0_b32 s4, 31
 ; GFX10-NEXT:    v_mul_f32_e64 v0, 0x3e4ccccd, s4
 ; GFX10-NEXT:  .LBB2_2: ; %exit
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
@@ -103,10 +103,10 @@ define float @fold_abs_in_branch_fabs(float %arg1, float %arg2) {
 ; GFX10-NEXT:    s_mov_b32 s4, exec_lo
 ; GFX10-NEXT:    v_add_f32_e32 v1, v0, v1
 ; GFX10-NEXT:    v_add_f32_e64 v0, |v1|, |v1|
+; GFX10-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v1
 ; GFX10-NEXT:    v_cmpx_nlt_f32_e32 1.0, v0
 ; GFX10-NEXT:  ; %bb.1: ; %if
-; GFX10-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v1
-; GFX10-NEXT:    v_mul_f32_e64 v0, 0x3e4ccccd, |v0|
+; GFX10-NEXT:    v_mul_f32_e64 v0, 0x3e4ccccd, |v1|
 ; GFX10-NEXT:  ; %bb.2: ; %exit
 ; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]