From: Daniel Schwierzeck Date: Sat, 11 Jul 2020 22:45:56 +0000 (+0200) Subject: mips: refactor disabling of caches X-Git-Tag: v2020.10~109^2~11 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=60772433dd42987f3b965188d9577150084b8956;p=platform%2Fkernel%2Fu-boot.git mips: refactor disabling of caches Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck Reviewed-by: Stefan Roese Tested-by: Stefan Roese --- diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index c3d1e64..a9f8743 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -196,11 +196,10 @@ wr_done: mtc0 zero, CP0_COMPARE #ifndef CONFIG_SKIP_LOWLEVEL_INIT - mfc0 t0, CP0_CONFIG - and t0, t0, MIPS_CONF_IMPL - or t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - ehb + /* Disable caches */ + PTR_LA t9, mips_cache_disable + jalr t9 + nop #endif #ifdef CONFIG_MIPS_CM diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 2233d27..602741c 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -418,6 +418,12 @@ return: jr R_RETURN END(mips_cache_reset) +LEAF(mips_cache_disable) + move R_RETURN, ra + change_k0_cca_kseg1 CONF_CM_UNCACHED + jr R_RETURN + END(mips_cache_disable) + LEAF(change_k0_cca) mfc0 t0, CP0_CONFIG #if __mips_isa_rev >= 2