From: Mylène Josserand Date: Tue, 17 Jan 2017 14:02:22 +0000 (+0100) Subject: clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig X-Git-Tag: v4.11-rc1~71^2~12^2~20 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=603a0c8af9cb23f7cf94d57e76113fef51848200;p=platform%2Fkernel%2Flinux-exynos.git clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 94f1c8b..0d513d2 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -440,7 +440,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", - 0x140, BIT(31), 0); + 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 0x140, BIT(30), 0); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",