From: Thomas Symalla <thomas.symalla@amd.com>
Date: Tue, 26 Jan 2021 10:26:50 +0000 (+0100)
Subject: Renamed med3 opcode, removed superfluous copy.
X-Git-Tag: llvmorg-14-init~16324
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=602896b9d2f27b1ea0fd1f78db51fee25d4f2de0;p=platform%2Fupstream%2Fllvm.git

Renamed med3 opcode, removed superfluous copy.
---

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 7e62fdf..76406f3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -175,7 +175,7 @@ def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>;
 def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
 
 def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>;
-def : GINodeEquiv<G_AMDGPU_MED3_S32, AMDGPUsmed3>;
+def : GINodeEquiv<G_AMDGPU_MED3, AMDGPUsmed3>;
 
 def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index 969be8f..c336b9e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -140,13 +140,12 @@ void AMDGPUPreLegalizerCombinerHelper::applyClampI64ToI16(
 
   auto Bitcast = B.buildBitcast({S32}, CvtPk);
 
-  auto Med3 = B.buildInstr(AMDGPU::G_AMDGPU_MED3_S32,
+  auto Med3 = B.buildInstr(AMDGPU::G_AMDGPU_MED3,
     {S32},
     {MinBoundaryDst.getReg(0), Bitcast.getReg(0), MaxBoundaryDst.getReg(0)},
     MI.getFlags());
   
-  auto Trunc = B.buildTrunc(LLT::scalar(16), Med3);
-  B.buildCopy(MI.getOperand(0).getReg(), Trunc);
+  B.buildTrunc(MI.getOperand(0).getReg(), Med3);
 
   MI.eraseFromParent();
 }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 8c1cac6..c9cca1e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3622,7 +3622,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
   case AMDGPU::G_AMDGPU_CVT_PK_I16_I32:
-  case AMDGPU::G_AMDGPU_MED3_S32:
+  case AMDGPU::G_AMDGPU_MED3:
     return getDefaultMappingVOP(MI);
   case AMDGPU::G_UMULH:
   case AMDGPU::G_SMULH: {
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 184f24d..92c0d19 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2581,7 +2581,7 @@ def G_AMDGPU_CVT_PK_I16_I32 : AMDGPUGenericInstruction {
   let hasSideEffects = 0;
 }
 
-def G_AMDGPU_MED3_S32 : AMDGPUGenericInstruction {
+def G_AMDGPU_MED3 : AMDGPUGenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
   let hasSideEffects = 0;