From: Simon Dardis Date: Wed, 20 Jun 2018 19:59:58 +0000 (+0000) Subject: [mips] Correct predicates for loads, bit manipulation instructions and some pseudos X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=6021424c102621097302215b8be4b49d5abbda08;p=platform%2Fupstream%2Fllvm.git [mips] Correct predicates for loads, bit manipulation instructions and some pseudos Additionally, correct the definition of the rdhwr instruction. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48216 llvm-svn: 335162 --- diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 5c18d5e..cd19f1c 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -776,7 +776,8 @@ let DecoderNamespace = "MicroMips" in { ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6; def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6; - def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>; + def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>, + ISA_MICROMIPS32_NOT_MIPS32R6; def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6; def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, @@ -1397,6 +1398,10 @@ let EncodingPredicates = [InMicroMips] in { def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>, ISA_MICROMIPS32_NOT_MIPS32R6; } +def : MipsInstAlias<"rdhwr $rt, $rs", + (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>, ISA_MICROMIPS32R5, ASE_VIRT; def : MipsInstAlias<"mfgc0 $rt, $rs", diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index 549f8b2..04bb710 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -508,6 +508,7 @@ class EXT_FM funct> : StdArch { class RDHWR_FM : StdArch { bits<5> rt; bits<5> rd; + bits<3> sel; bits<32> Inst; @@ -515,7 +516,8 @@ class RDHWR_FM : StdArch { let Inst{25-21} = 0; let Inst{20-16} = rt; let Inst{15-11} = rd; - let Inst{10-6} = 0; + let Inst{10-9} = 0b00; + let Inst{8-6} = sel; let Inst{5-0} = 0x3b; } diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 3271cd1..d4ab92b 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1824,8 +1824,8 @@ class SubwordSwap : - InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], - II_RDHWR, FrmR, "rdhwr">; + InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel), + "rdhwr\t$rt, $rd, $sel", [], II_RDHWR, FrmR, "rdhwr">; // Ext and Ins class ExtBase, ISA_MIPS32R2; + FrmR, opstr>; // 'ins' and its' 64 bit variants are matched by C++ code. class InsBase, ISA_MIPS32R2 { + II_INS, FrmR, opstr> { let Constraints = "$src = $rt"; } @@ -2050,19 +2050,20 @@ let AdditionalPredicates = [NotInMicroMips] in { /// aligned let AdditionalPredicates = [NotInMicroMips] in { def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel, - LW_FM<0x20>; + LW_FM<0x20>, ISA_MIPS1; def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU, - addrDefault>, MMRel, LW_FM<0x24>; + addrDefault>, MMRel, LW_FM<0x24>, ISA_MIPS1; def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH, - addrDefault>, MMRel, LW_FM<0x21>; + addrDefault>, MMRel, LW_FM<0x21>, ISA_MIPS1; def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>, - MMRel, LW_FM<0x25>; + MMRel, LW_FM<0x25>, ISA_MIPS1; def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, - LW_FM<0x23>; + LW_FM<0x23>, ISA_MIPS1; def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, - LW_FM<0x28>; - def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; - def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; + LW_FM<0x28>, ISA_MIPS1; + def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>, + ISA_MIPS1; + def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1; } /// load/store left/right @@ -2210,10 +2211,10 @@ let AdditionalPredicates = [NotInMicroMips] in { ISA_MIPS1_NOT_32R6_64R6; def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>, BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; - def BAL_BR : BAL_BR_Pseudo; + def BAL_BR : BAL_BR_Pseudo, ISA_MIPS1; } let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in { - def TAILCALL : TailCall; + def TAILCALL : TailCall, ISA_MIPS1; } let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, NoIndirectJumpGuards] in @@ -2357,15 +2358,15 @@ let AdditionalPredicates = [NotInMicroMips] in { 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; def PseudoUDIV : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; - def RDHWR : MMRel, ReadHardware, RDHWR_FM; + def RDHWR : MMRel, ReadHardware, RDHWR_FM, ISA_MIPS1; // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5, immZExt5Plus1, MipsExt>, - EXT_FM<0>; + EXT_FM<0>, ISA_MIPS32R2; def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, immZExt5, immZExt5Plus1>, - EXT_FM<4>; + EXT_FM<4>, ISA_MIPS32R2; } /// Move Control Registers From/To CPU Registers let AdditionalPredicates = [NotInMicroMips] in { @@ -2711,6 +2712,9 @@ let AdditionalPredicates = [NotInMicroMips] in { (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; + def : MipsInstAlias<"rdhwr $rt, $rs", + (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, ISA_MIPS1; + } def : MipsInstAlias<"sub, $rd, $rs, $imm", (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 97e9a83..599c1e9 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -976,9 +976,9 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } SDNode *Rdhwr = - CurDAG->getMachineNode(RdhwrOpc, DL, - Node->getValueType(0), - CurDAG->getRegister(Mips::HWR29, MVT::i32)); + CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), + CurDAG->getRegister(Mips::HWR29, MVT::i32), + CurDAG->getTargetConstant(0, DL, MVT::i32)); SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, SDValue(Rdhwr, 0)); SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir index d088172..ebe1183 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir @@ -157,7 +157,7 @@ body: | %0 = ADDu killed %8, killed %14 %15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard %16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard - %17 = RDHWR64 $hwr29 + %17 = RDHWR64 $hwr29, 0 $v1_64 = COPY %17 %18 = COPY $v1_64 %19 = DADDu %18, killed %16 @@ -170,7 +170,7 @@ body: | %32 = LUi64 target-flags(mips-tprel-hi) @k %33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k - %34 = RDHWR64 $hwr29 + %34 = RDHWR64 $hwr29, 0 $v1_64 = COPY %34 %35 = COPY $v1_64 %36 = DADDu %35, killed %33 @@ -182,7 +182,7 @@ body: | %21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard %22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard - %23 = RDHWR64 $hwr29 + %23 = RDHWR64 $hwr29, 0 $v1_64 = COPY %23 %24 = COPY $v1_64 %25 = DADDu %24, killed %22 @@ -222,7 +222,7 @@ body: | ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp bb.5._ZTW1j.exit: - %44 = RDHWR64 $hwr29 + %44 = RDHWR64 $hwr29, 0 $v1_64 = COPY %44 %45 = LD %43, target-flags(mips-gottprel) @j :: (load 8) %46 = COPY $v1_64 diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index 9d94426..a995c37 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -131,6 +131,7 @@ ori $9, $6, 17767 # CHECK: ori $9, $6, 17767 # encoding: [0x51,0x xor $3, $3, $5 # CHECK: xor $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x10] xori $9, $6, 17767 # CHECK: xori $9, $6, 17767 # encoding: [0x71,0x26,0x45,0x67] nor $9, $6, $7 # CHECK: nor $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0xd0] + # CHECK-NEXT: #