From: Tanner Gooding <tagoo@outlook.com>
Date: Thu, 29 Nov 2018 15:59:27 +0000 (-0800)
Subject: Updating genSIMDZero to only use `xorps` (#21249)
X-Git-Tag: accepted/tizen/unified/20190422.045933~511
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5feb0389f1e1ba715fba5560c979ac6362b1bcf8;p=platform%2Fupstream%2Fcoreclr.git

Updating genSIMDZero to only use `xorps` (#21249)
---

diff --git a/src/jit/simdcodegenxarch.cpp b/src/jit/simdcodegenxarch.cpp
index c0ecf25..0fd2d15 100644
--- a/src/jit/simdcodegenxarch.cpp
+++ b/src/jit/simdcodegenxarch.cpp
@@ -730,9 +730,11 @@ void CodeGen::genSIMDScalarMove(
 
 void CodeGen::genSIMDZero(var_types targetType, var_types baseType, regNumber targetReg)
 {
-    // pxor reg, reg
-    instruction ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType);
-    inst_RV_RV(ins, targetReg, targetReg, targetType, emitActualTypeSize(targetType));
+    // We just use `INS_xorps` instead of `getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType)`
+    // since `genSIMDZero` is used for both `System.Numerics.Vectors` and HardwareIntrinsics. Modern
+    // CPUs handle this specially in the renamer and it never hits the execution pipeline, additionally
+    // `INS_xorps` is always available (when using either the legacy or VEX encoding).
+    inst_RV_RV(INS_xorps, targetReg, targetReg, targetType, emitActualTypeSize(targetType));
 }
 
 //------------------------------------------------------------------------