From: Tapani Pälli <tapani.palli@intel.com>
Date: Mon, 6 Mar 2023 09:28:46 +0000 (+0200)
Subject: intel/isl: disable TILE64 for YCRCB formats
X-Git-Tag: upstream/23.3.3~11887
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5fdbc4a23e1a15b90e399a7586bece0b47e408d7;p=platform%2Fupstream%2Fmesa.git

intel/isl: disable TILE64 for YCRCB formats

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21723>
---

diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c
index 959139c..79d89c9 100644
--- a/src/intel/isl/isl_gfx12.c
+++ b/src/intel/isl/isl_gfx12.c
@@ -74,6 +74,13 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
    if (info->dim != ISL_SURF_DIM_2D)
       *flags &= ~ISL_TILING_64_BIT;
 
+   /* TILE64 does not work with YCRCB formats, according to bspec 58767:
+    * "Packed YUV surface formats such as YCRCB_NORMAL, YCRCB_SWAPUVY etc.
+    * will not support as Tile64"
+    */
+   if (isl_format_is_yuv(info->format))
+      *flags &= ~ISL_TILING_64_BIT;
+
    /* From RENDER_SURFACE_STATE::NumberofMultisamples,
     *
     *    This field must not be programmed to anything other than