From: uros Date: Mon, 14 Jan 2013 16:44:55 +0000 (+0000) Subject: PR target/55948 X-Git-Tag: upstream/4.9.2~8126 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5fc510c2456aa9f3ef4bf0f25dd24119b95eb6e4;p=platform%2Fupstream%2Flinaro-gcc.git PR target/55948 * config/i386/sync.md (atomic_store_1): New pattern. (atomic_store): Call atomic_store_1 for IX86_HLE_RELEASE memmodel flag. testsuite/ChangeLog PR target/55948 * gcc.target/i386/hle-clear-rel.c: New file * gcc.target/i386/hle-store-rel.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195155 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 64df290..0e37b98 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2012-01-14 Uros Bizjak + Andi Kleen + + PR target/55948 + * config/i386/sync.md (atomic_store_1): New pattern. + (atomic_store): Call atomic_store_1 for IX86_HLE_RELEASE + memmodel flag. + 2013-01-14 Georg-Johann Lay * config/avr/avr-stdint.h: Remove trailing blanks. @@ -7,7 +15,7 @@ * config/avr/avr-dimode.md: Same. * config/avr/predicates.md: Same. * config/avr/avr-c.c: Same. And fix typo. - + * config/avr/avr-protos.h: Same. And: (function_arg_regno_p): Rename to avr_function_arg_regno_p. (init_cumulative_args): Rename to avr_init_cumulative_args. diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 83198b9..2309c83 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -224,8 +224,12 @@ DONE; } - /* Otherwise use a normal store. */ - emit_move_insn (operands[0], operands[1]); + /* Otherwise use a store. */ + if (INTVAL (operands[2]) & IX86_HLE_RELEASE) + emit_insn (gen_atomic_store_1 (operands[0], operands[1], + operands[2])); + else + emit_move_insn (operands[0], operands[1]); } /* ... followed by an MFENCE, if required. */ if (model == MEMMODEL_SEQ_CST) @@ -233,6 +237,14 @@ DONE; }) +(define_insn "atomic_store_1" + [(set (match_operand:ATOMIC 0 "memory_operand" "=m") + (unspec:ATOMIC [(match_operand:ATOMIC 1 "" "") + (match_operand:SI 2 "const_int_operand")] + UNSPEC_MOVA))] + "" + "%K2mov{}\t{%1, %0|%0, %1}") + (define_insn_and_split "atomic_storedi_fpu" [(set (match_operand:DI 0 "memory_operand" "=m,m,m") (unspec:DI [(match_operand:DI 1 "register_operand" "x,m,?r")] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7384828..b9095dd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2012-01-14 Andi Kleen + + PR target/55948 + * gcc.target/i386/hle-clear-rel.c: New file + * gcc.target/i386/hle-store-rel.c: New file. + 2013-01-14 Harald Anlauf * gfortran.dg/aint_anint_1.f90: Add dg-do run. @@ -62,14 +68,13 @@ 2013-01-10 Richard Sandiford - Update copyright years + Update copyright years. 2013-01-10 Aldy Hernandez Jakub Jelinek PR target/55565 - * gcc.target/powerpc/ppc-mov-1.c: Update scan-assembler-not - regex. + * gcc.target/powerpc/ppc-mov-1.c: Update scan-assembler-not regex. 2013-01-10 Vladimir Makarov @@ -140,7 +145,7 @@ 2013-01-09 Jan Hubicka - PR tree-optimiation/55875 + PR tree-optimization/55875 * gcc.c-torture/execute/pr55875.c: New testcase. * g++.dg/torture/pr55875.C: New testcase. @@ -181,14 +186,14 @@ 2013-01-08 James Greenhalgh - * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New. - * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. - * gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. - * gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. - * gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. - * gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. - * gcc/testsuite/gcc.target/aarch64/vect-fcm.x: Likewise. - * gcc/testsuite/lib/target-supports.exp + * gcc.target/aarch64/vect-fcm-eq-d.c: New. + * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. + * gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. + * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. + * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. + * gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. + * gcc.target/aarch64/vect-fcm.x: Likewise. + * lib/target-supports.exp (check_effective_target_vect_cond): Enable for AArch64. 2013-01-08 James Greenhalgh diff --git a/gcc/testsuite/gcc.target/i386/hle-clear-rel.c b/gcc/testsuite/gcc.target/i386/hle-clear-rel.c new file mode 100644 index 0000000..137a820 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/hle-clear-rel.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */ + +void +hle_clear (char *p, int v) +{ + __atomic_clear (p, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/i386/hle-store-rel.c b/gcc/testsuite/gcc.target/i386/hle-store-rel.c new file mode 100644 index 0000000..7295d33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/hle-store-rel.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */ + +void +hle_store (int *p, int v) +{ + __atomic_store_n (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +}