From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Wed, 7 Sep 2016 09:56:11 +0000 (+0800)
Subject: armv8: ls1046a: Enable DDR erratum for ls1046a
X-Git-Tag: v2016.11-rc1~40^2~10
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5f5e8d92d56fb6d6bd792b067fe8931259d1b99a;p=platform%2Fkernel%2Fu-boot.git

armv8: ls1046a: Enable DDR erratum for ls1046a

Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b27087d..81a5e7c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -240,6 +240,12 @@
 #define GICC_BASE		0x01420000
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif