From: Grygorii Strashko <grygorii.strashko@ti.com>
Date: Mon, 18 Nov 2019 21:04:47 +0000 (+0200)
Subject: arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxid
X-Git-Tag: v2020.10~454^2~45
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5efb69298be40b1f277157b41e38442ab50eb4f2;p=platform%2Fkernel%2Fu-boot.git

arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxid

The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 8589f76..bea80c5 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -336,13 +336,12 @@
 		reg = <0>;
 		/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 	};
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-id";
+	phy-mode = "rgmii-rxid";
 	phy-handle = <&phy0>;
 };