From: Jiaxun Yang Date: Wed, 25 Mar 2020 03:54:58 +0000 (+0800) Subject: dt-bindings: interrupt-controller: Add Loongson-3 HTPIC X-Git-Tag: v5.15~4223^2~10 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5ef7ce7e81bbc1788a7e24d067f34f591a9508f1;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Document Loongson-3 HyperTransport PIC controller. Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml new file mode 100644 index 0000000..c8861cb --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 HyperTransport Interrupt Controller + +maintainers: + - Jiaxun Yang + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + This interrupt controller is found in the Loongson-3 family of chips to transmit + interrupts from PCH PIC connected on HyperTransport bus. + +properties: + compatible: + const: loongson,htpic-1.0 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 4 + description: | + Four parent interrupts that receive chained interrupts. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include + htintc: interrupt-controller@1fb000080 { + compatible = "loongson,htintc-1.0"; + reg = <0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +...