From: amodra Date: Tue, 9 Mar 2004 12:10:25 +0000 (+0000) Subject: * config/rs6000/rs6000.md: Remove trailing whitespace. X-Git-Tag: upstream/4.9.2~72437 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5e3715ccbe229c5a6a64f4cdff54355586832782;p=platform%2Fupstream%2Flinaro-gcc.git * config/rs6000/rs6000.md: Remove trailing whitespace. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@79166 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9bce157..43dc9cb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2004-03-09 Alan Modra + + * config/rs6000/rs6000.md: Remove trailing whitespace. + 2004-03-08 Eric Christopher * Makefile.in (site.exp): Add libiconv variable definition. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4acf056..4f95e21 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -67,7 +67,7 @@ (const_string "integer")) ;; Length (in bytes). -; '(pc)' in the following doesn't include the instruction itself; it is +; '(pc)' in the following doesn't include the instruction itself; it is ; calculated as if the instruction had zero size. (define_attr "length" "" (if_then_else (eq_attr "type" "branch") @@ -1632,7 +1632,7 @@ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }) - + (define_expand "ffssi2" [(set (match_dup 2) (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) @@ -1648,7 +1648,7 @@ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }) - + (define_expand "mulsi3" [(use (match_operand:SI 0 "gpc_reg_operand" "")) (use (match_operand:SI 1 "gpc_reg_operand" "")) @@ -1672,10 +1672,10 @@ "@ {muls|mullw} %0,%1,%2 {muli|mulli} %0,%1,%2" - [(set (attr "type") + [(set (attr "type") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") (const_string "imul3") - (match_operand:SI 2 "short_cint_operand" "") + (match_operand:SI 2 "short_cint_operand" "") (const_string "imul2")] (const_string "imul")))]) @@ -1687,10 +1687,10 @@ "@ {muls|mullw} %0,%1,%2 {muli|mulli} %0,%1,%2" - [(set (attr "type") + [(set (attr "type") (cond [(match_operand:SI 2 "s8bit_cint_operand" "") (const_string "imul3") - (match_operand:SI 2 "short_cint_operand" "") + (match_operand:SI 2 "short_cint_operand" "") (const_string "imul2")] (const_string "imul")))]) @@ -2568,7 +2568,7 @@ (const_int 0)))] "") -;; Split a logical operation that we can't do in one insn into two insns, +;; Split a logical operation that we can't do in one insn into two insns, ;; each of which does one 16-bit part. This is used by combine. (define_split @@ -4686,7 +4686,7 @@ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" [(const_int 0)] " -{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), +{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1], operands[2]); DONE; }") @@ -4879,7 +4879,7 @@ (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && ! HONOR_SIGNED_ZEROS (DFmode)" "{fnms|fnmsub} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -4892,7 +4892,7 @@ [(set_attr "type" "dsqrt")]) ;; The conditional move instructions allow us to perform max and min -;; operations even when +;; operations even when (define_expand "maxdf3" [(set (match_operand:DF 0 "gpc_reg_operand" "") @@ -4920,7 +4920,7 @@ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" [(const_int 0)] " -{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), +{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1], operands[2]); DONE; }") @@ -5046,7 +5046,7 @@ tmp = highword; highword = lowword; lowword = tmp; } - emit_insn (gen_xorsi3 (operands[6], operands[1], + emit_insn (gen_xorsi3 (operands[6], operands[1], GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); @@ -5642,7 +5642,7 @@ (define_insn "*ashrdisi3_noppc64" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 32)) 4))] "TARGET_32BIT && !TARGET_POWERPC64" "* @@ -5652,7 +5652,7 @@ else return \"mr %0,%1\"; }" - [(set_attr "length" "4")]) + [(set_attr "length" "4")]) ;; PowerPC64 DImode operations. @@ -6032,15 +6032,15 @@ (define_expand "ctzdi2" [(set (match_dup 2) (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) - (parallel [(set (match_dup 3) (and:DI (match_dup 1) - (match_dup 2))) + (parallel [(set (match_dup 3) (and:DI (match_dup 1) + (match_dup 2))) (clobber (scratch:CC))]) (set (match_dup 4) (clz:DI (match_dup 3))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (minus:DI (const_int 63) (match_dup 4)))] "TARGET_POWERPC64" { - operands[2] = gen_reg_rtx (DImode); + operands[2] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); }) @@ -6048,15 +6048,15 @@ (define_expand "ffsdi2" [(set (match_dup 2) (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) - (parallel [(set (match_dup 3) (and:DI (match_dup 1) - (match_dup 2))) + (parallel [(set (match_dup 3) (and:DI (match_dup 1) + (match_dup 2))) (clobber (scratch:CC))]) (set (match_dup 4) (clz:DI (match_dup 3))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (minus:DI (const_int 64) (match_dup 4)))] "TARGET_POWERPC64" { - operands[2] = gen_reg_rtx (DImode); + operands[2] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); }) @@ -6656,7 +6656,7 @@ "TARGET_POWERPC64" "sld%I2 %0,%1,%H2" [(set_attr "length" "8")]) - + (define_insn "*ashldi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") @@ -6669,7 +6669,7 @@ #" [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) - + (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7336,7 +7336,7 @@ (const_int 0)))] "") -;; Split a logical operation that we can't do in one insn into two insns, +;; Split a logical operation that we can't do in one insn into two insns, ;; each of which does one 16-bit part. This is used by combine. (define_split @@ -7350,7 +7350,7 @@ " { rtx i3,i4; - + if (GET_CODE (operands[2]) == CONST_DOUBLE) { HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); @@ -7578,7 +7578,7 @@ ;; Used by sched, shorten_branches and final when the GOT pseudo reg ;; didn't get allocated to a hard register. -(define_split +(define_split [(set (match_operand:SI 0 "gpc_reg_operand" "") (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") (match_operand:SI 2 "memory_operand" "")] @@ -7641,12 +7641,12 @@ return \"ld %0,lo16(%2)(%1)\"; else { - operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); + operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); #if TARGET_MACHO if (MACHO_DYNAMIC_NO_PIC_P) output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); - else + else /* We cannot rely on ha16(low half)==ha16(high half), alas, although in practice it almost always is. */ output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); @@ -8255,7 +8255,7 @@ emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), operands[2]); DONE; -}) +}) (define_expand "extendsftf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") @@ -8475,7 +8475,7 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "input_operand" ""))] - "reload_completed && !TARGET_POWERPC64 + "reload_completed && !TARGET_POWERPC64 && gpr_or_gpr_p (operands[0], operands[1])" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) @@ -8635,7 +8635,7 @@ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] - "TARGET_POWER && ! TARGET_POWERPC64 + "TARGET_POWER && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "* { @@ -8683,7 +8683,7 @@ case 3: /* If the address is not used in the output, we can use lsi. Otherwise, fall through to generating four loads. */ - if (TARGET_STRING + if (TARGET_STRING && ! reg_overlap_mentioned_p (operands[0], operands[1])) return \"{lsi|lswi} %0,%P1,16\"; /* ... fall through ... */ @@ -8699,8 +8699,8 @@ "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "@ - # - # + # + # #" [(set_attr "type" "*,load,store")]) @@ -9832,7 +9832,7 @@ if (current_function_limit_stack) { rtx available; - available = expand_binop (Pmode, sub_optab, + available = expand_binop (Pmode, sub_optab, stack_pointer_rtx, stack_limit_rtx, NULL_RTX, 1, OPTAB_WIDEN); emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); @@ -10393,7 +10393,7 @@ (match_operand 1 "" "g")) (use (match_operand:SI 2 "immediate_operand" "O")) (clobber (match_scratch:SI 3 "=l"))] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[2]) & CALL_LONG) == 0" "bl %z0\;%." @@ -10447,7 +10447,7 @@ (match_operand 2 "" "g"))) (use (match_operand:SI 3 "immediate_operand" "O")) (clobber (match_scratch:SI 4 "=l"))] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[3]) & CALL_LONG) == 0" "bl %z1\;%." @@ -10498,7 +10498,7 @@ return output_call(insn, operands, 0, 2); #else return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; -#endif +#endif } [(set_attr "type" "branch,branch") (set_attr "length" "4,8")]) @@ -10543,7 +10543,7 @@ return output_call(insn, operands, 1, 3); #else return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; -#endif +#endif } [(set_attr "type" "branch,branch") (set_attr "length" "4,8")]) @@ -10705,7 +10705,7 @@ (use (match_operand:SI 2 "immediate_operand" "O")) (use (match_operand:SI 3 "register_operand" "l")) (return)] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[2]) & CALL_LONG) == 0" "b %z0" @@ -10733,7 +10733,7 @@ (use (match_operand:SI 3 "immediate_operand" "O")) (use (match_operand:SI 4 "register_operand" "l")) (return)] - "TARGET_64BIT + "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && (INTVAL (operands[3]) & CALL_LONG) == 0" "b %z1" @@ -11010,11 +11010,11 @@ [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] "" " -{ +{ if (! rs6000_compare_fp_p) FAIL; - rs6000_emit_sCOND (NE, operands[0]); + rs6000_emit_sCOND (NE, operands[0]); DONE; }") @@ -11042,7 +11042,7 @@ && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; - rs6000_emit_sCOND (GT, operands[0]); + rs6000_emit_sCOND (GT, operands[0]); DONE; }") @@ -11056,7 +11056,7 @@ && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; - rs6000_emit_sCOND (LE, operands[0]); + rs6000_emit_sCOND (LE, operands[0]); DONE; }") @@ -11066,11 +11066,11 @@ "" " { - if (! rs6000_compare_fp_p + if (! rs6000_compare_fp_p && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) FAIL; - rs6000_emit_sCOND (LT, operands[0]); + rs6000_emit_sCOND (LT, operands[0]); DONE; }") @@ -13792,7 +13792,7 @@ }") (define_expand "tablejumpdi" - [(set (match_dup 4) + [(set (match_dup 4) (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) (set (match_dup 3) (plus:DI (match_dup 4) @@ -14364,7 +14364,7 @@ (define_insn "movesi_from_cr" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) + (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] UNSPEC_MOVESI_FROM_CR))] "" @@ -14377,7 +14377,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r"))])] "TARGET_MULTIPLE" "{stm|stmw} %2,%1") - + (define_insn "*save_fpregs_si" [(match_parallel 0 "any_operand" [(clobber (match_operand:SI 1 "register_operand" "=l")) @@ -14453,7 +14453,7 @@ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") (match_operand 2 "immediate_operand" "n")] UNSPEC_MOVESI_TO_CR))] - "GET_CODE (operands[0]) == REG + "GET_CODE (operands[0]) == REG && CR_REGNO_P (REGNO (operands[0])) && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" @@ -14470,7 +14470,7 @@ (match_operand:SI 2 "memory_operand" "m"))])] "TARGET_MULTIPLE" "{lm|lmw} %1,%2") - + (define_insn "*return_internal_si" [(return) (use (match_operand:SI 0 "register_operand" "lc"))]