From: Roman Lebedev Date: Tue, 30 Jul 2019 15:46:03 +0000 (+0000) Subject: [DivRemPairs] Add srem-of-srem tests (PR42823, D65298, D65451) X-Git-Tag: llvmorg-11-init~13285 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5e0adce40f3481246c887ccfe4bb67573539e5de;p=platform%2Fupstream%2Fllvm.git [DivRemPairs] Add srem-of-srem tests (PR42823, D65298, D65451) The @srem_of_srem_expanded case exposed a RAUW pitfall in D65298. Right now these don't appear to fail verification, so it should be safe to precommit them. https://reviews.llvm.org/D65298 https://bugs.llvm.org/show_bug.cgi?id=42823 https://reviews.llvm.org/D65451 llvm-svn: 367325 --- diff --git a/llvm/test/Transforms/DivRemPairs/PowerPC/div-expanded-rem-pair.ll b/llvm/test/Transforms/DivRemPairs/PowerPC/div-expanded-rem-pair.ll index aac9ad6..17865a9 100644 --- a/llvm/test/Transforms/DivRemPairs/PowerPC/div-expanded-rem-pair.ll +++ b/llvm/test/Transforms/DivRemPairs/PowerPC/div-expanded-rem-pair.ll @@ -95,6 +95,51 @@ end: ret i8 %ret } +; Be careful with RAUW/invalidation if this is a srem-of-srem. + +define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_unexpanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0]] +; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[X]], [[TMP1]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[TMP2]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[T4]], [[Y]] +; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: ret i32 [[TMP4]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3.recomposed = srem i32 %X, %t0 + %t4 = sdiv i32 %t3.recomposed, %Y + %t5 = mul nsw i32 %t4, %Y + %t6.recomposed = srem i32 %t3.recomposed, %Y + ret i32 %t6.recomposed +} +define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_expanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]] +; CHECK-NEXT: ret i32 [[T6]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3 = sub nsw i32 %X, %t2 + %t4 = sdiv i32 %t3, %Y + %t5 = mul nsw i32 %t4, %Y + %t6 = sub nsw i32 %t3, %t5 + ret i32 %t6 +} + ; If the target doesn't have a unified div/rem op for the type, keep decomposed rem define i128 @dont_hoist_urem(i128 %a, i128 %b) { diff --git a/llvm/test/Transforms/DivRemPairs/PowerPC/div-rem-pairs.ll b/llvm/test/Transforms/DivRemPairs/PowerPC/div-rem-pairs.ll index c82360c..b3636cd 100644 --- a/llvm/test/Transforms/DivRemPairs/PowerPC/div-rem-pairs.ll +++ b/llvm/test/Transforms/DivRemPairs/PowerPC/div-rem-pairs.ll @@ -151,6 +151,51 @@ end: ret i8 %ret } +; Be careful with RAUW/invalidation if this is a srem-of-srem. + +define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_unexpanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0]] +; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[X]], [[TMP1]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[TMP2]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[T4]], [[Y]] +; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: ret i32 [[TMP4]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3.recomposed = srem i32 %X, %t0 + %t4 = sdiv i32 %t3.recomposed, %Y + %t5 = mul nsw i32 %t4, %Y + %t6.recomposed = srem i32 %t3.recomposed, %Y + ret i32 %t6.recomposed +} +define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_expanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]] +; CHECK-NEXT: ret i32 [[T6]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3 = sub nsw i32 %X, %t2 + %t4 = sdiv i32 %t3, %Y + %t5 = mul nsw i32 %t4, %Y + %t6 = sub nsw i32 %t3, %t5 + ret i32 %t6 +} + ; If the ops don't match, don't do anything: signedness. define i32 @dont_hoist_udiv(i32 %a, i32 %b) { diff --git a/llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll b/llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll index a38d6c9..005b859 100644 --- a/llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll +++ b/llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll @@ -95,6 +95,49 @@ end: ret i8 %ret } +; Be careful with RAUW/invalidation if this is a srem-of-srem. + +define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_unexpanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]] +; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3.recomposed = srem i32 %X, %t0 + %t4 = sdiv i32 %t3.recomposed, %Y + %t5 = mul nsw i32 %t4, %Y + %t6.recomposed = srem i32 %t3.recomposed, %Y + ret i32 %t6.recomposed +} +define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_expanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]] +; CHECK-NEXT: ret i32 [[T6]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3 = sub nsw i32 %X, %t2 + %t4 = sdiv i32 %t3, %Y + %t5 = mul nsw i32 %t4, %Y + %t6 = sub nsw i32 %t3, %t5 + ret i32 %t6 +} + ; If the target doesn't have a unified div/rem op for the type, keep decomposed rem define i128 @dont_hoist_urem(i128 %a, i128 %b) { diff --git a/llvm/test/Transforms/DivRemPairs/X86/div-rem-pairs.ll b/llvm/test/Transforms/DivRemPairs/X86/div-rem-pairs.ll index 74c8e6e..ed772ad 100644 --- a/llvm/test/Transforms/DivRemPairs/X86/div-rem-pairs.ll +++ b/llvm/test/Transforms/DivRemPairs/X86/div-rem-pairs.ll @@ -145,6 +145,49 @@ end: ret i8 %ret } +; Be careful with RAUW/invalidation if this is a srem-of-srem. + +define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_unexpanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]] +; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3.recomposed = srem i32 %X, %t0 + %t4 = sdiv i32 %t3.recomposed, %Y + %t5 = mul nsw i32 %t4, %Y + %t6.recomposed = srem i32 %t3.recomposed, %Y + ret i32 %t6.recomposed +} +define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) { +; CHECK-LABEL: @srem_of_srem_expanded( +; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]] +; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]] +; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]] +; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]] +; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]] +; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]] +; CHECK-NEXT: ret i32 [[T6]] +; + %t0 = mul nsw i32 %Z, %Y + %t1 = sdiv i32 %X, %t0 + %t2 = mul nsw i32 %t0, %t1 + %t3 = sub nsw i32 %X, %t2 + %t4 = sdiv i32 %t3, %Y + %t5 = mul nsw i32 %t4, %Y + %t6 = sub nsw i32 %t3, %t5 + ret i32 %t6 +} + ; If the ops don't match, don't do anything: signedness. define i32 @dont_hoist_udiv(i32 %a, i32 %b) {