From: Kenneth Graunke Date: Wed, 8 Aug 2012 16:41:19 +0000 (-0700) Subject: i965: Rework the extra flushes surrounding occlusion queries. X-Git-Tag: mesa-9.0~653 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5deb1d1a1f9e3354597569032af9bdf27d629cca;p=platform%2Fupstream%2Fmesa.git i965: Rework the extra flushes surrounding occlusion queries. This removes the CS stall on Ivybridge. On Sandybridge, the depth stall needs to be preceded by a non-zero post-sync op, which requires a CS stall, which needs a stall at scoreboard. Emit the full workaround. Reviewed-by: Daniel Vetter Cc: Eric Anholt Signed-off-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 1e03d08..b39f644 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -91,14 +91,11 @@ static void write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx) { if (intel->gen >= 6) { - BEGIN_BATCH(9); - - /* workaround: CS stall required before depth stall. */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(PIPE_CONTROL_CS_STALL); - OUT_BATCH(0); /* write address */ - OUT_BATCH(0); /* write data */ + /* Emit Sandybridge workaround flush: */ + if (intel->gen == 6) + intel_emit_post_sync_nonzero_flush(intel); + BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT);