From: Samuel Iglesias Gonsálvez Date: Tue, 22 Sep 2020 15:28:43 +0000 (+0200) Subject: Fix wrong access flag for depth/stencil resolve X-Git-Tag: upstream/1.3.5~1194 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5dc2e5a676f86fe930156339a435fca9603a33b4;p=platform%2Fupstream%2FVK-GL-CTS.git Fix wrong access flag for depth/stencil resolve According to the spec: "End-of-subpass multisample resolves are treated as color attachment writes for the purposes of synchronization." Affects: dEQP-VK.renderpass2.depth_stencil_resolve.* Component: Vulkan VK-GL-CTS issue: 2593 Change-Id: I055049fffc0fd4bdbd162c4468cf80ff0c5ca373 --- diff --git a/external/vulkancts/modules/vulkan/renderpass/vktRenderPassDepthStencilResolveTests.cpp b/external/vulkancts/modules/vulkan/renderpass/vktRenderPassDepthStencilResolveTests.cpp index 6647034..dd44021 100644 --- a/external/vulkancts/modules/vulkan/renderpass/vktRenderPassDepthStencilResolveTests.cpp +++ b/external/vulkancts/modules/vulkan/renderpass/vktRenderPassDepthStencilResolveTests.cpp @@ -858,7 +858,7 @@ void DepthStencilResolveTest::submit (void) VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, DE_NULL, - VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, + VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, VK_ACCESS_TRANSFER_READ_BIT, VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL,