From: Peter Maydell <peter.maydell@linaro.org>
Date: Wed, 12 Oct 2016 17:54:33 +0000 (+0100)
Subject: target-arm: Implement dummy MDCCINT_EL1
X-Git-Tag: TizenStudio_2.0_p2.3.2~9^2~14^2~5^2~124^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5dbdc4342f479d799a1970dd5fd22e64c9dcd50d;p=sdk%2Femulator%2Fqemu.git

target-arm: Implement dummy MDCCINT_EL1

MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1476294876-12340-2-git-send-email-peter.maydell@linaro.org
---

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 70e2742..a65f4f2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tda,
       .type = ARM_CP_NOP },
+    /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
+     * Channel but Linux may try to access this register. The 32-bit
+     * alias is DBGDCCINT.
+     */
+    { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
+      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .accessfn = access_tda,
+      .type = ARM_CP_NOP },
     REGINFO_SENTINEL
 };