From: Tom Stellard <thomas.stellard@amd.com>
Date: Mon, 29 Aug 2016 13:06:10 +0000 (+0000)
Subject: AMDGPU/SI: Improve register allocation hints for sopk instructions
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5d3f71f721273e17412dcb3a1726235aabc65651;p=platform%2Fupstream%2Fllvm.git

AMDGPU/SI: Improve register allocation hints for sopk instructions

Summary:
For shrinking SOPK instructions, we were creating a hint to tell the
register allocator to use the register allocated for src0 for the dst
operand as well.  However, this seems to not work sometimes depending
on the order virtual registers are assigned physical registers.

To fix this, I've added a second allocation hint which does the reverse,
asks that the register allocated for dst is used for src0.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D23862

llvm-svn: 279968
---

diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index c791dd3..9f1c9b0 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -282,6 +282,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
         if (TargetRegisterInfo::isVirtualRegister(Dest.getReg()) &&
             Src0.isReg()) {
           MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());
+          MRI.setRegAllocationHint(Src0.getReg(), 0, Dest.getReg());
           continue;
         }
 
diff --git a/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll b/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
index 13254d0..9b5f9fe 100644
--- a/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
@@ -74,8 +74,8 @@ define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) #
 ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
 ; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]]
-; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
+; SI: s_addk_i32 [[TMP]], 0x3d8
+; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]
 ; SI: buffer_store_dword [[VRESULT]]
 
 define void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {