From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Sun, 30 May 2021 17:18:37 +0000 (+0530)
Subject: asahi: Implement wide lines
X-Git-Tag: upstream/21.2.3~2696
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5c97d1c83704107e4977fbabbcf63176cd0ec101;p=platform%2Fupstream%2Fmesa.git

asahi: Implement wide lines

Identify line width field and route through the Gallium line width.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
---

diff --git a/src/asahi/lib/cmdbuf.xml b/src/asahi/lib/cmdbuf.xml
index 83e793b..74c2795 100644
--- a/src/asahi/lib/cmdbuf.xml
+++ b/src/asahi/lib/cmdbuf.xml
@@ -176,7 +176,8 @@
 
   <struct name="Rasterizer face" size="8">
     <field name="Stencil reference" size="8" start="0:0" type="hex" default="0x00"/>
-    <field name="Unk 1" size="8" start="0:8" type="hex" default="0xF"/>
+    <!-- line width is 4:4 fixed point with off-by-one applied -->
+    <field name="Line width" size="8" start="0:8" type="hex" default="0xF"/>
     <field name="Polygon mode" size="2" start="0:18" type="Polygon Mode" default="Fill"/>
     <field name="Disable depth write" size="1" start="0:21" type="bool"/>
     <field name="Depth function" size="3" start="0:24" type="ZS Func" default="Always"/>
diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c
index fd61ef3..c25e6f7 100644
--- a/src/gallium/drivers/asahi/agx_pipe.c
+++ b/src/gallium/drivers/asahi/agx_pipe.c
@@ -709,7 +709,7 @@ agx_get_paramf(struct pipe_screen* pscreen,
    switch (param) {
    case PIPE_CAPF_MAX_LINE_WIDTH:
    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
-      return 255.0; /* arbitrary */
+      return 16.0; /* Off-by-one fixed point 4:4 encoding */
 
    case PIPE_CAPF_MAX_POINT_WIDTH:
    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index b978803..ff93f74 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -154,6 +154,12 @@ agx_create_rs_state(struct pipe_context *ctx,
    struct agx_rasterizer *so = CALLOC_STRUCT(agx_rasterizer);
    so->base = *cso;
 
+   /* Line width is packed in a 4:4 fixed point format */
+   unsigned line_width_fixed = ((unsigned) (cso->line_width * 16.0f)) - 1;
+
+   /* Clamp to maximum line width */
+   so->line_width = MIN2(line_width_fixed, 0xFF);
+
    agx_pack(so->cull, CULL, cfg) {
       cfg.cull_front = cso->cull_face & PIPE_FACE_FRONT;
       cfg.cull_back = cso->cull_face & PIPE_FACE_BACK;
@@ -1091,11 +1097,14 @@ static uint64_t
 demo_rasterizer(struct agx_context *ctx, struct agx_pool *pool)
 {
    struct agx_ptr t = agx_pool_alloc_aligned(pool, AGX_RASTERIZER_LENGTH, 64);
+   struct agx_rasterizer *rast = ctx->rast;
 
    agx_pack(t.cpu, RASTERIZER, cfg) {
       cfg.front.depth_function = ctx->zs.z_func;
       cfg.back.depth_function = ctx->zs.z_func;
 
+      cfg.front.line_width = cfg.back.line_width = rast->line_width;
+
       cfg.front.disable_depth_write = ctx->zs.disable_z_write;
       cfg.back.disable_depth_write = ctx->zs.disable_z_write;
 
diff --git a/src/gallium/drivers/asahi/agx_state.h b/src/gallium/drivers/asahi/agx_state.h
index 420eeec..220708d 100644
--- a/src/gallium/drivers/asahi/agx_state.h
+++ b/src/gallium/drivers/asahi/agx_state.h
@@ -159,6 +159,7 @@ agx_context(struct pipe_context *pctx)
 struct agx_rasterizer {
    struct pipe_rasterizer_state base;
    uint8_t cull[AGX_CULL_LENGTH];
+   uint8_t line_width;
 };
 
 struct agx_query {