From: Chia-I Wu Date: Sat, 24 Jan 2015 04:49:28 +0000 (+0800) Subject: intel: fix DEPTH_STENCIL_STATE on Gen6 X-Git-Tag: sdk-0.1.0~779 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5bdb096ea3f2f5e6d80533746128c8bc9ad5ca0a;p=platform%2Fupstream%2FVulkan-LoaderAndValidationLayers.git intel: fix DEPTH_STENCIL_STATE on Gen6 pipeline_build_depth_stencil() should be called on all Gens. --- diff --git a/icd/intel/pipeline.c b/icd/intel/pipeline.c index 067be2f..f4cd5a2 100644 --- a/icd/intel/pipeline.c +++ b/icd/intel/pipeline.c @@ -1207,6 +1207,7 @@ static XGL_RESULT pipeline_build_all(struct intel_pipeline *pipeline, pipeline_build_vertex_elements(pipeline, info); pipeline_build_fragment_SBE(pipeline); pipeline_build_msaa(pipeline, info); + pipeline_build_depth_stencil(pipeline, info); if (intel_gpu_gen(pipeline->dev->gpu) >= INTEL_GEN(7)) { pipeline_build_urb_alloc_gen7(pipeline, info); @@ -1215,7 +1216,6 @@ static XGL_RESULT pipeline_build_all(struct intel_pipeline *pipeline, pipeline_build_hs(pipeline, info); pipeline_build_te(pipeline, info); pipeline_build_ds(pipeline, info); - pipeline_build_depth_stencil(pipeline, info); pipeline->wa_flags = INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE | INTEL_CMD_WA_GEN6_PRE_COMMAND_SCOREBOARD_STALL |