From: wernsaar Date: Fri, 8 Nov 2013 08:08:11 +0000 (+0100) Subject: added blas level1 dot kernels for complex and double complex X-Git-Tag: v0.2.9.rc1~7^2~6^2~54 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5b36cc0f4725e4cff6f818dd7de4690a9a28c15a;p=platform%2Fupstream%2Fopenblas.git added blas level1 dot kernels for complex and double complex --- diff --git a/kernel/arm/KERNEL.ARMV7 b/kernel/arm/KERNEL.ARMV7 index 7387be1..a6b1d67 100644 --- a/kernel/arm/KERNEL.ARMV7 +++ b/kernel/arm/KERNEL.ARMV7 @@ -52,8 +52,8 @@ ZCOPYKERNEL = zcopy_vfpv3.S SDOTKERNEL = sdot_vfpv3.S DDOTKERNEL = ddot_vfpv3.S -CDOTKERNEL = ../arm/zdot.c -ZDOTKERNEL = ../arm/zdot.c +CDOTKERNEL = cdot_vfpv3.S +ZDOTKERNEL = zdot_vfpv3.S SNRM2KERNEL = ../arm/nrm2.c DNRM2KERNEL = ../arm/nrm2.c diff --git a/kernel/arm/cdot_vfpv3.S b/kernel/arm/cdot_vfpv3.S new file mode 100644 index 0000000..2618089 --- /dev/null +++ b/kernel/arm/cdot_vfpv3.S @@ -0,0 +1,284 @@ +/*************************************************************************** +Copyright (c) 2013, The OpenBLAS Project +All rights reserved. +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: +1. Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +3. Neither the name of the OpenBLAS project nor the names of +its contributors may be used to endorse or promote products +derived from this software without specific prior written permission. +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +/************************************************************************************** +* 2013/11/08 Saar +* BLASTEST : OK +* CTEST : OK +* TEST : OK +* +**************************************************************************************/ + +#define ASSEMBLER +#include "common.h" + +#define STACKSIZE 256 + +#define N r0 +#define X r1 +#define INC_X r2 +#define OLD_Y r3 + + +/****************************************************** +* [fp, #-128] - [fp, #-64] is reserved +* for store and restore of floating point +* registers +*******************************************************/ + +#define OLD_INC_Y [fp, #4 ] + +#define I r5 +#define Y r6 +#define INC_Y r7 + +#define X_PRE 256 + +/************************************************************************************** +* Macro definitions +**************************************************************************************/ + +.macro KERNEL_F4 + + pld [ X, #X_PRE ] + pld [ Y, #X_PRE ] + + fldmias X!, { s4 - s5 } + fldmias Y!, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fldmias X!, { s6 - s7 } + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + + fldmias Y!, { s10 - s11 } + fmacs s0 , s6, s10 + fmacs s1 , s6, s11 + fmacs s2 , s7, s11 + fmacs s3 , s7, s10 + + + fldmias X!, { s4 - s5 } + fldmias Y!, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fldmias X!, { s6 - s7 } + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + + fldmias Y!, { s10 - s11 } + fmacs s0 , s6, s10 + fmacs s1 , s6, s11 + fmacs s2 , s7, s11 + fmacs s3 , s7, s10 + +.endm + +.macro KERNEL_F1 + + fldmias X!, { s4 - s5 } + fldmias Y!, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + +.endm + + +/*************************************************************************************************************************/ + +.macro KERNEL_S4 + + nop + + fldmias X, { s4 - s5 } + fldmias Y, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + add X, X, INC_X + add Y, Y, INC_Y + + fldmias X, { s4 - s5 } + fldmias Y, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + add X, X, INC_X + add Y, Y, INC_Y + + fldmias X, { s4 - s5 } + fldmias Y, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + add X, X, INC_X + add Y, Y, INC_Y + + fldmias X, { s4 - s5 } + fldmias Y, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + add X, X, INC_X + add Y, Y, INC_Y + +.endm + + +.macro KERNEL_S1 + + fldmias X, { s4 - s5 } + fldmias Y, { s8 - s9 } + fmacs s0 , s4, s8 + fmacs s1 , s4, s9 + fmacs s2 , s5, s9 + fmacs s3 , s5, s8 + add X, X, INC_X + add Y, Y, INC_Y + +.endm + + + +/************************************************************************************** +* End of macro definitions +**************************************************************************************/ + + PROLOGUE + + .align 5 + + push {r4 - r9, fp} + add fp, sp, #24 + sub sp, sp, #STACKSIZE // reserve stack + + sub r4, fp, #128 + vstm r4, { s8 - s15} // store floating point registers + + mov Y, OLD_Y + ldr INC_Y, OLD_INC_Y + + vsub.f32 s0 , s0 , s0 + vsub.f32 s1 , s1 , s1 + vsub.f32 s2 , s2 , s2 + vsub.f32 s3 , s3 , s3 + + cmp N, #0 + ble cdot_kernel_L999 + + cmp INC_X, #0 + beq cdot_kernel_L999 + + cmp INC_Y, #0 + beq cdot_kernel_L999 + + cmp INC_X, #1 + bne cdot_kernel_S_BEGIN + + cmp INC_Y, #1 + bne cdot_kernel_S_BEGIN + +cdot_kernel_F_BEGIN: + + asrs I, N, #2 // I = N / 4 + ble cdot_kernel_F1 + +cdot_kernel_F4: + + KERNEL_F4 + + subs I, I, #1 + bne cdot_kernel_F4 + +cdot_kernel_F1: + + ands I, N, #3 + ble cdot_kernel_L999 + +cdot_kernel_F10: + + KERNEL_F1 + + subs I, I, #1 + bne cdot_kernel_F10 + + b cdot_kernel_L999 + +cdot_kernel_S_BEGIN: + + lsl INC_X, INC_X, #3 // INC_X * SIZE * 2 + lsl INC_Y, INC_Y, #3 // INC_Y * SIZE * 2 + + asrs I, N, #2 // I = N / 4 + ble cdot_kernel_S1 + +cdot_kernel_S4: + + KERNEL_S4 + + subs I, I, #1 + bne cdot_kernel_S4 + +cdot_kernel_S1: + + ands I, N, #3 + ble cdot_kernel_L999 + +cdot_kernel_S10: + + KERNEL_S1 + + subs I, I, #1 + bne cdot_kernel_S10 + + + +cdot_kernel_L999: + + sub r3, fp, #128 + vldm r3, { s8 - s15} // restore floating point registers + +#if !defined(CONJ) + vsub.f32 s0 , s0, s2 + vadd.f32 s1 , s1, s3 +#else + vadd.f32 s0 , s0, s2 + vsub.f32 s1 , s1, s3 +#endif + + sub sp, fp, #24 + pop {r4 - r9, fp} + bx lr + + EPILOGUE + diff --git a/kernel/arm/zdot_vfpv3.S b/kernel/arm/zdot_vfpv3.S new file mode 100644 index 0000000..2aa9171 --- /dev/null +++ b/kernel/arm/zdot_vfpv3.S @@ -0,0 +1,286 @@ +/*************************************************************************** +Copyright (c) 2013, The OpenBLAS Project +All rights reserved. +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: +1. Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +3. Neither the name of the OpenBLAS project nor the names of +its contributors may be used to endorse or promote products +derived from this software without specific prior written permission. +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +/************************************************************************************** +* 2013/11/08 Saar +* BLASTEST : OK +* CTEST : OK +* TEST : OK +* +**************************************************************************************/ + +#define ASSEMBLER +#include "common.h" + +#define STACKSIZE 256 + +#define N r0 +#define X r1 +#define INC_X r2 +#define OLD_Y r3 + + +/****************************************************** +* [fp, #-128] - [fp, #-64] is reserved +* for store and restore of floating point +* registers +*******************************************************/ + +#define OLD_INC_Y [fp, #4 ] + +#define I r5 +#define Y r6 +#define INC_Y r7 + +#define X_PRE 256 + +/************************************************************************************** +* Macro definitions +**************************************************************************************/ + +.macro KERNEL_F4 + + pld [ X, #X_PRE ] + pld [ Y, #X_PRE ] + + fldmiad X!, { d4 - d5 } + fldmiad Y!, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fldmiad X!, { d6 - d7 } + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + + fldmiad Y!, { d10 - d11 } + fmacd d0 , d6, d10 + fmacd d1 , d6, d11 + pld [ X, #X_PRE ] + fmacd d2 , d7, d11 + fmacd d3 , d7, d10 + + pld [ Y, #X_PRE ] + + fldmiad X!, { d4 - d5 } + fldmiad Y!, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fldmiad X!, { d6 - d7 } + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + + fldmiad Y!, { d10 - d11 } + fmacd d0 , d6, d10 + fmacd d1 , d6, d11 + fmacd d2 , d7, d11 + fmacd d3 , d7, d10 + +.endm + +.macro KERNEL_F1 + + fldmiad X!, { d4 - d5 } + fldmiad Y!, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + +.endm + + +/*************************************************************************************************************************/ + +.macro KERNEL_S4 + + nop + + fldmiad X, { d4 - d5 } + fldmiad Y, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + add X, X, INC_X + add Y, Y, INC_Y + + fldmiad X, { d4 - d5 } + fldmiad Y, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + add X, X, INC_X + add Y, Y, INC_Y + + fldmiad X, { d4 - d5 } + fldmiad Y, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + add X, X, INC_X + add Y, Y, INC_Y + + fldmiad X, { d4 - d5 } + fldmiad Y, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + add X, X, INC_X + add Y, Y, INC_Y + +.endm + + +.macro KERNEL_S1 + + fldmiad X, { d4 - d5 } + fldmiad Y, { d8 - d9 } + fmacd d0 , d4, d8 + fmacd d1 , d4, d9 + fmacd d2 , d5, d9 + fmacd d3 , d5, d8 + add X, X, INC_X + add Y, Y, INC_Y + +.endm + + + +/************************************************************************************** +* End of macro definitions +**************************************************************************************/ + + PROLOGUE + + .align 5 + + push {r4 - r9, fp} + add fp, sp, #24 + sub sp, sp, #STACKSIZE // reserve stack + + sub r4, fp, #128 + vstm r4, { d8 - d15} // store floating point registers + + mov Y, OLD_Y + ldr INC_Y, OLD_INC_Y + + vsub.f64 d0 , d0 , d0 + vsub.f64 d1 , d1 , d1 + vsub.f64 d2 , d2 , d2 + vsub.f64 d3 , d3 , d3 + + cmp N, #0 + ble zdot_kernel_L999 + + cmp INC_X, #0 + beq zdot_kernel_L999 + + cmp INC_Y, #0 + beq zdot_kernel_L999 + + cmp INC_X, #1 + bne zdot_kernel_S_BEGIN + + cmp INC_Y, #1 + bne zdot_kernel_S_BEGIN + +zdot_kernel_F_BEGIN: + + asrs I, N, #2 // I = N / 4 + ble zdot_kernel_F1 + +zdot_kernel_F4: + + KERNEL_F4 + + subs I, I, #1 + bne zdot_kernel_F4 + +zdot_kernel_F1: + + ands I, N, #3 + ble zdot_kernel_L999 + +zdot_kernel_F10: + + KERNEL_F1 + + subs I, I, #1 + bne zdot_kernel_F10 + + b zdot_kernel_L999 + +zdot_kernel_S_BEGIN: + + lsl INC_X, INC_X, #4 // INC_X * SIZE * 2 + lsl INC_Y, INC_Y, #4 // INC_Y * SIZE * 2 + + asrs I, N, #2 // I = N / 4 + ble zdot_kernel_S1 + +zdot_kernel_S4: + + KERNEL_S4 + + subs I, I, #1 + bne zdot_kernel_S4 + +zdot_kernel_S1: + + ands I, N, #3 + ble zdot_kernel_L999 + +zdot_kernel_S10: + + KERNEL_S1 + + subs I, I, #1 + bne zdot_kernel_S10 + + + +zdot_kernel_L999: + + sub r3, fp, #128 + vldm r3, { d8 - d15} // restore floating point registers + +#if !defined(CONJ) + vsub.f64 d0 , d0, d2 + vadd.f64 d1 , d1, d3 +#else + vadd.f64 d0 , d0, d2 + vsub.f64 d1 , d1, d3 +#endif + + sub sp, fp, #24 + pop {r4 - r9, fp} + bx lr + + EPILOGUE +