From: Eugene O'Brien <eugene.obrien@advantechamt.com>
Date: Fri, 11 Apr 2008 14:00:35 +0000 (-0400)
Subject: ppc4xx: Fix power mgt definitions for PPC440
X-Git-Tag: v2008.10-rc1~495^2~3^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5b2052e5f5fcce5dbd4d2750a29c0e45bce806e7;hp=64e541f4c1b413dd84c7e409f5c2bf328db2ac13;p=platform%2Fkernel%2Fu-boot.git

ppc4xx: Fix power mgt definitions for PPC440

Corrected DCR addresses of PPC440EP power management registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
---

diff --git a/include/ppc440.h b/include/ppc440.h
index 642d1de..bb39ad6 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1731,17 +1731,10 @@
 #else
 #define CNTRL_DCR_BASE 0x0b0
 #endif
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
 #define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable register		*/
 #define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force register		*/
 #define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status register		*/
-#else
-#define cpc0_sr		(CNTRL_DCR_BASE+0x00)	/* CPM status register		*/
-#define cpc0_er		(CNTRL_DCR_BASE+0x01)	/* CPM enable register		*/
-#define cpc0_fr		(CNTRL_DCR_BASE+0x02)	/* CPM force register		*/
-#endif
 
 #define cpc0_sys0	(CNTRL_DCR_BASE+0x30)	/* System configuration reg 0	*/
 #define cpc0_sys1	(CNTRL_DCR_BASE+0x31)	/* System configuration reg 1	*/