From: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Date: Tue, 29 Aug 2017 04:56:26 +0000 (+0200)
Subject: nir/spirv: fix chain access with different index bit sizes
X-Git-Tag: upstream/18.1.0~6136
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5b1b088f2a176973b66e0765b4127c7882a12860;p=platform%2Fupstream%2Fmesa.git

nir/spirv: fix chain access with different index bit sizes

Currently we support 32-bit indexes/offsets all over the driver, so we
convert them to that bit size.

Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.*

v2: Use u2u32 instead (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c
index e03547c..997b66f 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -102,10 +102,15 @@ vtn_access_link_as_ssa(struct vtn_builder *b, struct vtn_access_link link,
    if (link.mode == vtn_access_mode_literal) {
       return nir_imm_int(&b->nb, link.id * stride);
    } else if (stride == 1) {
-      return vtn_ssa_value(b, link.id)->def;
+       nir_ssa_def *ssa = vtn_ssa_value(b, link.id)->def;
+       if (ssa->bit_size != 32)
+          ssa = nir_u2u32(&b->nb, ssa);
+      return ssa;
    } else {
-      return nir_imul(&b->nb, vtn_ssa_value(b, link.id)->def,
-                              nir_imm_int(&b->nb, stride));
+      nir_ssa_def *src0 = vtn_ssa_value(b, link.id)->def;
+      if (src0->bit_size != 32)
+         src0 = nir_u2u32(&b->nb, src0);
+      return nir_imul(&b->nb, src0, nir_imm_int(&b->nb, stride));
    }
 }