From: Petar Avramovic Date: Mon, 25 Mar 2019 11:23:41 +0000 (+0000) Subject: [MIPS GlobalISel] Lower float and double arguments in registers X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5a457e08f6f94eea0470c8edc0d71a636a928d42;p=platform%2Fupstream%2Fllvm.git [MIPS GlobalISel] Lower float and double arguments in registers Lower float and double arguments in registers for MIPS32. When float/double argument is passed through gpr registers select appropriate move instruction. Differential Revision: https://reviews.llvm.org/D59642 llvm-svn: 356882 --- diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index fd0f7921..0cee6e7 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -23,10 +23,10 @@ using namespace llvm; MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI) : CallLowering(&TLI) {} -bool MipsCallLowering::MipsHandler::assign(unsigned VReg, - const CCValAssign &VA) { +bool MipsCallLowering::MipsHandler::assign(unsigned VReg, const CCValAssign &VA, + const EVT &VT) { if (VA.isRegLoc()) { - assignValueToReg(VReg, VA); + assignValueToReg(VReg, VA, VT); } else if (VA.isMemLoc()) { assignValueToAddress(VReg, VA); } else { @@ -37,9 +37,10 @@ bool MipsCallLowering::MipsHandler::assign(unsigned VReg, bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef VRegs, ArrayRef ArgLocs, - unsigned ArgLocsStartIndex) { + unsigned ArgLocsStartIndex, + const EVT &VT) { for (unsigned i = 0; i < VRegs.size(); ++i) - if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i])) + if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT)) return false; return true; } @@ -71,10 +72,10 @@ bool MipsCallLowering::MipsHandler::handle( for (unsigned i = 0; i < SplitLength; ++i) VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); - if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg)) + if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg, VT)) return false; } else { - if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex])) + if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex], VT)) return false; } } @@ -88,7 +89,8 @@ public: : MipsHandler(MIRBuilder, MRI) {} private: - void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override; + void assignValueToReg(unsigned ValVReg, const CCValAssign &VA, + const EVT &VT) override; unsigned getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) override; @@ -97,7 +99,7 @@ private: bool handleSplit(SmallVectorImpl &VRegs, ArrayRef ArgLocs, unsigned ArgLocsStartIndex, - unsigned ArgsReg) override; + unsigned ArgsReg, const EVT &VT) override; virtual void markPhysRegUsed(unsigned PhysReg) { MIRBuilder.getMBB().addLiveIn(PhysReg); @@ -127,21 +129,47 @@ private: } // end anonymous namespace void IncomingValueHandler::assignValueToReg(unsigned ValVReg, - const CCValAssign &VA) { + const CCValAssign &VA, + const EVT &VT) { + const MipsSubtarget &STI = + static_cast(MIRBuilder.getMF().getSubtarget()); unsigned PhysReg = VA.getLocReg(); - switch (VA.getLocInfo()) { - case CCValAssign::LocInfo::SExt: - case CCValAssign::LocInfo::ZExt: - case CCValAssign::LocInfo::AExt: { - auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); - MIRBuilder.buildTrunc(ValVReg, Copy); - break; - } - default: - MIRBuilder.buildCopy(ValVReg, PhysReg); - break; + if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { + const MipsSubtarget &STI = + static_cast(MIRBuilder.getMF().getSubtarget()); + + MIRBuilder + .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64 + : Mips::BuildPairF64) + .addDef(ValVReg) + .addUse(PhysReg + (STI.isLittle() ? 0 : 1)) + .addUse(PhysReg + (STI.isLittle() ? 1 : 0)) + .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), + *STI.getRegBankInfo()); + markPhysRegUsed(PhysReg); + markPhysRegUsed(PhysReg + 1); + } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { + MIRBuilder.buildInstr(Mips::MTC1) + .addDef(ValVReg) + .addUse(PhysReg) + .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), + *STI.getRegBankInfo()); + markPhysRegUsed(PhysReg); + } else { + switch (VA.getLocInfo()) { + case CCValAssign::LocInfo::SExt: + case CCValAssign::LocInfo::ZExt: + case CCValAssign::LocInfo::AExt: { + auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); + MIRBuilder.buildTrunc(ValVReg, Copy); + break; + } + default: + MIRBuilder.buildCopy(ValVReg, PhysReg); + break; + } + markPhysRegUsed(PhysReg); } - markPhysRegUsed(PhysReg); } unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA, @@ -180,8 +208,8 @@ void IncomingValueHandler::assignValueToAddress(unsigned ValVReg, bool IncomingValueHandler::handleSplit(SmallVectorImpl &VRegs, ArrayRef ArgLocs, unsigned ArgLocsStartIndex, - unsigned ArgsReg) { - if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex)) + unsigned ArgsReg, const EVT &VT) { + if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT)) return false; setLeastSignificantFirst(VRegs); MIRBuilder.buildMerge(ArgsReg, VRegs); @@ -196,7 +224,8 @@ public: : MipsHandler(MIRBuilder, MRI), MIB(MIB) {} private: - void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override; + void assignValueToReg(unsigned ValVReg, const CCValAssign &VA, + const EVT &VT) override; unsigned getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) override; @@ -205,7 +234,7 @@ private: bool handleSplit(SmallVectorImpl &VRegs, ArrayRef ArgLocs, unsigned ArgLocsStartIndex, - unsigned ArgsReg) override; + unsigned ArgsReg, const EVT &VT) override; unsigned extendRegister(unsigned ValReg, const CCValAssign &VA); @@ -214,11 +243,40 @@ private: } // end anonymous namespace void OutgoingValueHandler::assignValueToReg(unsigned ValVReg, - const CCValAssign &VA) { + const CCValAssign &VA, + const EVT &VT) { unsigned PhysReg = VA.getLocReg(); - unsigned ExtReg = extendRegister(ValVReg, VA); - MIRBuilder.buildCopy(PhysReg, ExtReg); - MIB.addUse(PhysReg, RegState::Implicit); + const MipsSubtarget &STI = + static_cast(MIRBuilder.getMF().getSubtarget()); + + if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { + MIRBuilder + .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 + : Mips::ExtractElementF64) + .addDef(PhysReg + (STI.isLittle() ? 1 : 0)) + .addUse(ValVReg) + .addImm(1) + .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), + *STI.getRegBankInfo()); + MIRBuilder + .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 + : Mips::ExtractElementF64) + .addDef(PhysReg + (STI.isLittle() ? 0 : 1)) + .addUse(ValVReg) + .addImm(0) + .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), + *STI.getRegBankInfo()); + } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { + MIRBuilder.buildInstr(Mips::MFC1) + .addDef(PhysReg) + .addUse(ValVReg) + .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), + *STI.getRegBankInfo()); + } else { + unsigned ExtReg = extendRegister(ValVReg, VA); + MIRBuilder.buildCopy(PhysReg, ExtReg); + MIB.addUse(PhysReg, RegState::Implicit); + } } unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA, @@ -286,10 +344,10 @@ unsigned OutgoingValueHandler::extendRegister(unsigned ValReg, bool OutgoingValueHandler::handleSplit(SmallVectorImpl &VRegs, ArrayRef ArgLocs, unsigned ArgLocsStartIndex, - unsigned ArgsReg) { + unsigned ArgsReg, const EVT &VT) { MIRBuilder.buildUnmerge(VRegs, ArgsReg); setLeastSignificantFirst(VRegs); - if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex)) + if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT)) return false; return true; @@ -300,6 +358,8 @@ static bool isSupportedType(Type *T) { return true; if (T->isPointerTy()) return true; + if (T->isFloatingPointTy()) + return true; return false; } diff --git a/llvm/lib/Target/Mips/MipsCallLowering.h b/llvm/lib/Target/Mips/MipsCallLowering.h index dc04d83..05c703b 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.h +++ b/llvm/lib/Target/Mips/MipsCallLowering.h @@ -35,7 +35,7 @@ public: protected: bool assignVRegs(ArrayRef VRegs, ArrayRef ArgLocs, - unsigned Index); + unsigned ArgLocsStartIndex, const EVT &VT); void setLeastSignificantFirst(SmallVectorImpl &VRegs); @@ -43,19 +43,21 @@ public: MachineRegisterInfo &MRI; private: - bool assign(unsigned VReg, const CCValAssign &VA); + bool assign(unsigned VReg, const CCValAssign &VA, const EVT &VT); virtual unsigned getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) = 0; - virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) = 0; + virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA, + const EVT &VT) = 0; virtual void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) = 0; virtual bool handleSplit(SmallVectorImpl &VRegs, ArrayRef ArgLocs, - unsigned ArgLocsStartIndex, unsigned ArgsReg) = 0; + unsigned ArgLocsStartIndex, unsigned ArgsReg, + const EVT &VT) = 0; }; MipsCallLowering(const MipsTargetLowering &TLI); diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll new file mode 100644 index 0000000..24cfcd8 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll @@ -0,0 +1,211 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py + +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 + +define float @float_in_fpr(float %a, float %b) { + ; FP32-LABEL: name: float_in_fpr + ; FP32: bb.1.entry: + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14 + ; FP32: $f0 = COPY [[COPY1]](s32) + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: float_in_fpr + ; FP64: bb.1.entry: + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14 + ; FP64: $f0 = COPY [[COPY1]](s32) + ; FP64: RetRA implicit $f0 +entry: + ret float %b +} + +define double @double_in_fpr(double %a, double %b) { + ; FP32-LABEL: name: double_in_fpr + ; FP32: bb.1.entry: + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7 + ; FP32: $d0 = COPY [[COPY1]](s64) + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: double_in_fpr + ; FP64: bb.1.entry: + ; FP64: liveins: $d12_64, $d14_64 + ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64 + ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64 + ; FP64: $d0_64 = COPY [[COPY1]](s64) + ; FP64: RetRA implicit $d0_64 +entry: + ret double %b +} + +define float @float_in_gpr(i32 %a, float %b) { + ; FP32-LABEL: name: float_in_gpr + ; FP32: bb.1.entry: + ; FP32: liveins: $a0, $a1 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1 + ; FP32: $f0 = COPY [[MTC1_]](s32) + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: float_in_gpr + ; FP64: bb.1.entry: + ; FP64: liveins: $a0, $a1 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1 + ; FP64: $f0 = COPY [[MTC1_]](s32) + ; FP64: RetRA implicit $f0 +entry: + ret float %b +} + +define double @double_in_gpr(i32 %a, double %b) { + ; FP32-LABEL: name: double_in_gpr + ; FP32: bb.1.entry: + ; FP32: liveins: $a0, $a2, $a3 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3 + ; FP32: $d0 = COPY [[BuildPairF64_]](s64) + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: double_in_gpr + ; FP64: bb.1.entry: + ; FP64: liveins: $a0, $a2, $a3 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 $a2, $a3 + ; FP64: $d0_64 = COPY [[BuildPairF64_64_]](s64) + ; FP64: RetRA implicit $d0_64 +entry: + ret double %b +} + +define float @call_float_in_fpr(float %a, float %b) { + ; FP32-LABEL: name: call_float_in_fpr + ; FP32: bb.1.entry: + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14 + ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP32: $f12 = COPY [[COPY]](s32) + ; FP32: $f14 = COPY [[COPY1]](s32) + ; FP32: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0 + ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0 + ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP32: $f0 = COPY [[COPY2]](s32) + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: call_float_in_fpr + ; FP64: bb.1.entry: + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14 + ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP64: $f12 = COPY [[COPY]](s32) + ; FP64: $f14 = COPY [[COPY1]](s32) + ; FP64: JAL @float_in_fpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0 + ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0 + ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP64: $f0 = COPY [[COPY2]](s32) + ; FP64: RetRA implicit $f0 +entry: + %call = call float @float_in_fpr(float %a, float %b) + ret float %call +} + +define double @call_double_in_fpr(double %a, double %b) { + ; FP32-LABEL: name: call_double_in_fpr + ; FP32: bb.1.entry: + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7 + ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP32: $d6 = COPY [[COPY]](s64) + ; FP32: $d7 = COPY [[COPY1]](s64) + ; FP32: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0 + ; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0 + ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP32: $d0 = COPY [[COPY2]](s64) + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: call_double_in_fpr + ; FP64: bb.1.entry: + ; FP64: liveins: $d12_64, $d14_64 + ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64 + ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64 + ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP64: $d12_64 = COPY [[COPY]](s64) + ; FP64: $d14_64 = COPY [[COPY1]](s64) + ; FP64: JAL @double_in_fpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit $d14_64, implicit-def $d0_64 + ; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64 + ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP64: $d0_64 = COPY [[COPY2]](s64) + ; FP64: RetRA implicit $d0_64 +entry: + %call = call double @double_in_fpr(double %a, double %b) + ret double %call +} + +define float @call_float_in_gpr(i32 %a, float %b) { + ; FP32-LABEL: name: call_float_in_gpr + ; FP32: bb.1.entry: + ; FP32: liveins: $a0, $a1 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1 + ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP32: $a0 = COPY [[COPY]](s32) + ; FP32: $a1 = MFC1 [[MTC1_]](s32) + ; FP32: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0 + ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0 + ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP32: $f0 = COPY [[COPY1]](s32) + ; FP32: RetRA implicit $f0 + ; FP64-LABEL: name: call_float_in_gpr + ; FP64: bb.1.entry: + ; FP64: liveins: $a0, $a1 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1 + ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP64: $a0 = COPY [[COPY]](s32) + ; FP64: $a1 = MFC1 [[MTC1_]](s32) + ; FP64: JAL @float_in_gpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0 + ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0 + ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP64: $f0 = COPY [[COPY1]](s32) + ; FP64: RetRA implicit $f0 +entry: + %call = call float @float_in_gpr(i32 %a, float %b) + ret float %call +} + + +define double @call_double_in_gpr(i32 %a, double %b) { + ; FP32-LABEL: name: call_double_in_gpr + ; FP32: bb.1.entry: + ; FP32: liveins: $a0, $a2, $a3 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3 + ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP32: $a0 = COPY [[COPY]](s32) + ; FP32: $a3 = ExtractElementF64 [[BuildPairF64_]](s64), 1 + ; FP32: $a2 = ExtractElementF64 [[BuildPairF64_]](s64), 0 + ; FP32: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0 + ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0 + ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP32: $d0 = COPY [[COPY1]](s64) + ; FP32: RetRA implicit $d0 + ; FP64-LABEL: name: call_double_in_gpr + ; FP64: bb.1.entry: + ; FP64: liveins: $a0, $a2, $a3 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 $a2, $a3 + ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; FP64: $a0 = COPY [[COPY]](s32) + ; FP64: $a3 = ExtractElementF64_64 [[BuildPairF64_64_]](s64), 1 + ; FP64: $a2 = ExtractElementF64_64 [[BuildPairF64_64_]](s64), 0 + ; FP64: JAL @double_in_gpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0_64 + ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64 + ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; FP64: $d0_64 = COPY [[COPY1]](s64) + ; FP64: RetRA implicit $d0_64 +entry: + %call = call double @double_in_gpr(i32 %a, double %b) + ret double %call +}