From: Simon Pilgrim Date: Sat, 1 Apr 2023 15:09:52 +0000 (+0100) Subject: [X86] Add vector-reduce-and-scalar.ll to test and(extract(v,0),extract(v,1)) style... X-Git-Tag: upstream/17.0.6~12971 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5a1d08b85442d61bbad958af2563f16efc08f396;p=platform%2Fupstream%2Fllvm.git [X86] Add vector-reduce-and-scalar.ll to test and(extract(v,0),extract(v,1)) style reduction patterns --- diff --git a/llvm/test/CodeGen/X86/vector-reduce-and-scalar.ll b/llvm/test/CodeGen/X86/vector-reduce-and-scalar.ll new file mode 100644 index 0000000..113b066 --- /dev/null +++ b/llvm/test/CodeGen/X86/vector-reduce-and-scalar.ll @@ -0,0 +1,1325 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL + +; +; vXi64 +; + +define i1 @test_v2i64(ptr %ptr) nounwind { +; SSE2-LABEL: test_v2i64: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: andq (%rdi), %rax +; SSE2-NEXT: cmpq $-1, %rax +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v2i64: +; SSE41: # %bb.0: +; SSE41-NEXT: movq (%rdi), %rax +; SSE41-NEXT: andq 8(%rdi), %rax +; SSE41-NEXT: cmpq $-1, %rax +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v2i64: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rax +; AVX-NEXT: andq 8(%rdi), %rax +; AVX-NEXT: cmpq $-1, %rax +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <2 x i64>, ptr %ptr + %v0 = extractelement <2 x i64> %vload, i32 0 + %v1 = extractelement <2 x i64> %vload, i32 1 + %vreduce = and i64 %v0, %v1 + %vcheck = icmp eq i64 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v4i64(ptr %ptr) nounwind { +; SSE2-LABEL: test_v4i64: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rcx +; SSE2-NEXT: andq (%rdi), %rax +; SSE2-NEXT: andq 16(%rdi), %rcx +; SSE2-NEXT: andq %rax, %rcx +; SSE2-NEXT: cmpq $-1, %rcx +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v4i64: +; SSE41: # %bb.0: +; SSE41-NEXT: movq (%rdi), %rax +; SSE41-NEXT: movq 16(%rdi), %rcx +; SSE41-NEXT: andq 8(%rdi), %rax +; SSE41-NEXT: andq 24(%rdi), %rcx +; SSE41-NEXT: andq %rax, %rcx +; SSE41-NEXT: cmpq $-1, %rcx +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v4i64: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rax +; AVX-NEXT: movq 16(%rdi), %rcx +; AVX-NEXT: andq 8(%rdi), %rax +; AVX-NEXT: andq 24(%rdi), %rcx +; AVX-NEXT: andq %rax, %rcx +; AVX-NEXT: cmpq $-1, %rcx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <4 x i64>, ptr %ptr + %v0 = extractelement <4 x i64> %vload, i32 0 + %v1 = extractelement <4 x i64> %vload, i32 1 + %v2 = extractelement <4 x i64> %vload, i32 2 + %v3 = extractelement <4 x i64> %vload, i32 3 + %vreduce01 = and i64 %v0, %v1 + %vreduce23 = and i64 %v2, %v3 + %vreduce = and i64 %vreduce01, %vreduce23 + %vcheck = icmp eq i64 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v8i64(ptr %ptr) nounwind { +; SSE2-LABEL: test_v8i64: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rcx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rdx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rsi +; SSE2-NEXT: andq (%rdi), %rax +; SSE2-NEXT: andq 16(%rdi), %rcx +; SSE2-NEXT: andq %rax, %rcx +; SSE2-NEXT: andq 32(%rdi), %rdx +; SSE2-NEXT: andq 48(%rdi), %rsi +; SSE2-NEXT: andq %rdx, %rsi +; SSE2-NEXT: andq %rcx, %rsi +; SSE2-NEXT: cmpq $-1, %rsi +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v8i64: +; SSE41: # %bb.0: +; SSE41-NEXT: movq 48(%rdi), %rax +; SSE41-NEXT: movq 32(%rdi), %rcx +; SSE41-NEXT: movq (%rdi), %rdx +; SSE41-NEXT: movq 16(%rdi), %rsi +; SSE41-NEXT: andq 8(%rdi), %rdx +; SSE41-NEXT: andq 24(%rdi), %rsi +; SSE41-NEXT: andq %rdx, %rsi +; SSE41-NEXT: andq 40(%rdi), %rcx +; SSE41-NEXT: andq 56(%rdi), %rax +; SSE41-NEXT: andq %rcx, %rax +; SSE41-NEXT: andq %rsi, %rax +; SSE41-NEXT: cmpq $-1, %rax +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v8i64: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rax +; AVX-NEXT: movq 16(%rdi), %rcx +; AVX-NEXT: movq 32(%rdi), %rdx +; AVX-NEXT: movq 48(%rdi), %rsi +; AVX-NEXT: andq 8(%rdi), %rax +; AVX-NEXT: andq 24(%rdi), %rcx +; AVX-NEXT: andq %rax, %rcx +; AVX-NEXT: andq 40(%rdi), %rdx +; AVX-NEXT: andq 56(%rdi), %rsi +; AVX-NEXT: andq %rdx, %rsi +; AVX-NEXT: andq %rcx, %rsi +; AVX-NEXT: cmpq $-1, %rsi +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <8 x i64>, ptr %ptr + %v0 = extractelement <8 x i64> %vload, i32 0 + %v1 = extractelement <8 x i64> %vload, i32 1 + %v2 = extractelement <8 x i64> %vload, i32 2 + %v3 = extractelement <8 x i64> %vload, i32 3 + %v4 = extractelement <8 x i64> %vload, i32 4 + %v5 = extractelement <8 x i64> %vload, i32 5 + %v6 = extractelement <8 x i64> %vload, i32 6 + %v7 = extractelement <8 x i64> %vload, i32 7 + %vreduce01 = and i64 %v0, %v1 + %vreduce23 = and i64 %v2, %v3 + %vreduce45 = and i64 %v4, %v5 + %vreduce67 = and i64 %v6, %v7 + %vreduce0123 = and i64 %vreduce01, %vreduce23 + %vreduce4567 = and i64 %vreduce45, %vreduce67 + %vreduce = and i64 %vreduce0123, %vreduce4567 + %vcheck = icmp eq i64 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v16i64(ptr %ptr) nounwind { +; SSE2-LABEL: test_v16i64: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rsi +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %r8 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %r9 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %r10 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rcx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %r11 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rdx +; SSE2-NEXT: andq (%rdi), %rsi +; SSE2-NEXT: andq 16(%rdi), %r8 +; SSE2-NEXT: andq %rsi, %r8 +; SSE2-NEXT: andq 32(%rdi), %r9 +; SSE2-NEXT: andq 48(%rdi), %rax +; SSE2-NEXT: andq %r9, %rax +; SSE2-NEXT: andq %r8, %rax +; SSE2-NEXT: andq 64(%rdi), %r10 +; SSE2-NEXT: andq 80(%rdi), %rcx +; SSE2-NEXT: andq %r10, %rcx +; SSE2-NEXT: andq 96(%rdi), %r11 +; SSE2-NEXT: andq 112(%rdi), %rdx +; SSE2-NEXT: andq %r11, %rdx +; SSE2-NEXT: andq %rcx, %rdx +; SSE2-NEXT: andq %rax, %rdx +; SSE2-NEXT: cmpq $-1, %rdx +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v16i64: +; SSE41: # %bb.0: +; SSE41-NEXT: movq 112(%rdi), %rax +; SSE41-NEXT: movq 96(%rdi), %rsi +; SSE41-NEXT: movq 80(%rdi), %rdx +; SSE41-NEXT: movq 64(%rdi), %r8 +; SSE41-NEXT: movq 48(%rdi), %rcx +; SSE41-NEXT: movq 32(%rdi), %r9 +; SSE41-NEXT: movq (%rdi), %r10 +; SSE41-NEXT: movq 16(%rdi), %r11 +; SSE41-NEXT: andq 8(%rdi), %r10 +; SSE41-NEXT: andq 24(%rdi), %r11 +; SSE41-NEXT: andq %r10, %r11 +; SSE41-NEXT: andq 40(%rdi), %r9 +; SSE41-NEXT: andq 56(%rdi), %rcx +; SSE41-NEXT: andq %r9, %rcx +; SSE41-NEXT: andq %r11, %rcx +; SSE41-NEXT: andq 72(%rdi), %r8 +; SSE41-NEXT: andq 88(%rdi), %rdx +; SSE41-NEXT: andq %r8, %rdx +; SSE41-NEXT: andq 104(%rdi), %rsi +; SSE41-NEXT: andq 120(%rdi), %rax +; SSE41-NEXT: andq %rsi, %rax +; SSE41-NEXT: andq %rdx, %rax +; SSE41-NEXT: andq %rcx, %rax +; SSE41-NEXT: cmpq $-1, %rax +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v16i64: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rdx +; AVX-NEXT: movq 16(%rdi), %rsi +; AVX-NEXT: movq 32(%rdi), %r8 +; AVX-NEXT: movq 48(%rdi), %rax +; AVX-NEXT: movq 64(%rdi), %r9 +; AVX-NEXT: movq 80(%rdi), %r10 +; AVX-NEXT: movq 96(%rdi), %r11 +; AVX-NEXT: movq 112(%rdi), %rcx +; AVX-NEXT: andq 8(%rdi), %rdx +; AVX-NEXT: andq 24(%rdi), %rsi +; AVX-NEXT: andq %rdx, %rsi +; AVX-NEXT: andq 40(%rdi), %r8 +; AVX-NEXT: andq 56(%rdi), %rax +; AVX-NEXT: andq %r8, %rax +; AVX-NEXT: andq %rsi, %rax +; AVX-NEXT: andq 72(%rdi), %r9 +; AVX-NEXT: andq 88(%rdi), %r10 +; AVX-NEXT: andq %r9, %r10 +; AVX-NEXT: andq 104(%rdi), %r11 +; AVX-NEXT: andq 120(%rdi), %rcx +; AVX-NEXT: andq %r11, %rcx +; AVX-NEXT: andq %r10, %rcx +; AVX-NEXT: andq %rax, %rcx +; AVX-NEXT: cmpq $-1, %rcx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <16 x i64>, ptr %ptr + %v0 = extractelement <16 x i64> %vload, i32 0 + %v1 = extractelement <16 x i64> %vload, i32 1 + %v2 = extractelement <16 x i64> %vload, i32 2 + %v3 = extractelement <16 x i64> %vload, i32 3 + %v4 = extractelement <16 x i64> %vload, i32 4 + %v5 = extractelement <16 x i64> %vload, i32 5 + %v6 = extractelement <16 x i64> %vload, i32 6 + %v7 = extractelement <16 x i64> %vload, i32 7 + %v8 = extractelement <16 x i64> %vload, i32 8 + %v9 = extractelement <16 x i64> %vload, i32 9 + %v10 = extractelement <16 x i64> %vload, i32 10 + %v11 = extractelement <16 x i64> %vload, i32 11 + %v12 = extractelement <16 x i64> %vload, i32 12 + %v13 = extractelement <16 x i64> %vload, i32 13 + %v14 = extractelement <16 x i64> %vload, i32 14 + %v15 = extractelement <16 x i64> %vload, i32 15 + %vreduce01 = and i64 %v0, %v1 + %vreduce23 = and i64 %v2, %v3 + %vreduce45 = and i64 %v4, %v5 + %vreduce67 = and i64 %v6, %v7 + %vreduce89 = and i64 %v8, %v9 + %vreduce1011 = and i64 %v10, %v11 + %vreduce1213 = and i64 %v12, %v13 + %vreduce1415 = and i64 %v14, %v15 + %vreduce0123 = and i64 %vreduce01, %vreduce23 + %vreduce4567 = and i64 %vreduce45, %vreduce67 + %vreduce891011 = and i64 %vreduce89, %vreduce1011 + %vreduce12131415 = and i64 %vreduce1213, %vreduce1415 + %vreduce01234567 = and i64 %vreduce0123, %vreduce4567 + %vreduce89101112131415 = and i64 %vreduce891011, %vreduce12131415 + %vreduce = and i64 %vreduce01234567, %vreduce89101112131415 + %vcheck = icmp eq i64 %vreduce, -1 + ret i1 %vcheck +} + +; +; vXi32 +; + +define i1 @test_v2i32(ptr %ptr) nounwind { +; SSE2-LABEL: test_v2i32: +; SSE2: # %bb.0: +; SSE2-NEXT: movq (%rdi), %rax +; SSE2-NEXT: movq %rax, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: andl %eax, %ecx +; SSE2-NEXT: cmpl $-1, %ecx +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v2i32: +; SSE41: # %bb.0: +; SSE41-NEXT: movq (%rdi), %rax +; SSE41-NEXT: movq %rax, %rcx +; SSE41-NEXT: shrq $32, %rcx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: cmpl $-1, %ecx +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v2i32: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rax +; AVX-NEXT: movq %rax, %rcx +; AVX-NEXT: shrq $32, %rcx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: cmpl $-1, %ecx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <2 x i32>, ptr %ptr + %v0 = extractelement <2 x i32> %vload, i32 0 + %v1 = extractelement <2 x i32> %vload, i32 1 + %vreduce = and i32 %v0, %v1 + %vcheck = icmp eq i32 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v4i32(ptr %ptr) nounwind { +; SSE2-LABEL: test_v4i32: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa (%rdi), %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; SSE2-NEXT: movd %xmm1, %ecx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %edx +; SSE2-NEXT: andl %ecx, %edx +; SSE2-NEXT: andl (%rdi), %eax +; SSE2-NEXT: andl %edx, %eax +; SSE2-NEXT: cmpl $-1, %eax +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v4i32: +; SSE41: # %bb.0: +; SSE41-NEXT: movl (%rdi), %eax +; SSE41-NEXT: movl 8(%rdi), %ecx +; SSE41-NEXT: andl 4(%rdi), %eax +; SSE41-NEXT: andl 12(%rdi), %ecx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: cmpl $-1, %ecx +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v4i32: +; AVX: # %bb.0: +; AVX-NEXT: movl (%rdi), %eax +; AVX-NEXT: movl 8(%rdi), %ecx +; AVX-NEXT: andl 4(%rdi), %eax +; AVX-NEXT: andl 12(%rdi), %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: cmpl $-1, %ecx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <4 x i32>, ptr %ptr + %v0 = extractelement <4 x i32> %vload, i32 0 + %v1 = extractelement <4 x i32> %vload, i32 1 + %v2 = extractelement <4 x i32> %vload, i32 2 + %v3 = extractelement <4 x i32> %vload, i32 3 + %vreduce01 = and i32 %v0, %v1 + %vreduce23 = and i32 %v2, %v3 + %vreduce = and i32 %vreduce01, %vreduce23 + %vcheck = icmp eq i32 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v8i32(ptr %ptr) nounwind { +; SSE2-LABEL: test_v8i32: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa (%rdi), %xmm0 +; SSE2-NEXT: movdqa 16(%rdi), %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,1,1] +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3] +; SSE2-NEXT: movd %xmm2, %ecx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %edx +; SSE2-NEXT: andl %ecx, %edx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] +; SSE2-NEXT: movd %xmm0, %esi +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %r8d +; SSE2-NEXT: andl %esi, %r8d +; SSE2-NEXT: andl (%rdi), %eax +; SSE2-NEXT: andl %edx, %eax +; SSE2-NEXT: andl 16(%rdi), %ecx +; SSE2-NEXT: andl %r8d, %ecx +; SSE2-NEXT: andl %eax, %ecx +; SSE2-NEXT: cmpl $-1, %ecx +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v8i32: +; SSE41: # %bb.0: +; SSE41-NEXT: movl 24(%rdi), %eax +; SSE41-NEXT: movl 16(%rdi), %ecx +; SSE41-NEXT: movl (%rdi), %edx +; SSE41-NEXT: movl 8(%rdi), %esi +; SSE41-NEXT: andl 4(%rdi), %edx +; SSE41-NEXT: andl 12(%rdi), %esi +; SSE41-NEXT: andl %edx, %esi +; SSE41-NEXT: andl 20(%rdi), %ecx +; SSE41-NEXT: andl 28(%rdi), %eax +; SSE41-NEXT: andl %ecx, %eax +; SSE41-NEXT: andl %esi, %eax +; SSE41-NEXT: cmpl $-1, %eax +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v8i32: +; AVX: # %bb.0: +; AVX-NEXT: movl (%rdi), %eax +; AVX-NEXT: movl 8(%rdi), %ecx +; AVX-NEXT: movl 24(%rdi), %edx +; AVX-NEXT: movl 16(%rdi), %esi +; AVX-NEXT: andl 4(%rdi), %eax +; AVX-NEXT: andl 12(%rdi), %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: andl 20(%rdi), %esi +; AVX-NEXT: andl 28(%rdi), %edx +; AVX-NEXT: andl %esi, %edx +; AVX-NEXT: andl %ecx, %edx +; AVX-NEXT: cmpl $-1, %edx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <8 x i32>, ptr %ptr + %v0 = extractelement <8 x i32> %vload, i32 0 + %v1 = extractelement <8 x i32> %vload, i32 1 + %v2 = extractelement <8 x i32> %vload, i32 2 + %v3 = extractelement <8 x i32> %vload, i32 3 + %v4 = extractelement <8 x i32> %vload, i32 4 + %v5 = extractelement <8 x i32> %vload, i32 5 + %v6 = extractelement <8 x i32> %vload, i32 6 + %v7 = extractelement <8 x i32> %vload, i32 7 + %vreduce01 = and i32 %v0, %v1 + %vreduce23 = and i32 %v2, %v3 + %vreduce45 = and i32 %v4, %v5 + %vreduce67 = and i32 %v6, %v7 + %vreduce0123 = and i32 %vreduce01, %vreduce23 + %vreduce4567 = and i32 %vreduce45, %vreduce67 + %vreduce = and i32 %vreduce0123, %vreduce4567 + %vcheck = icmp eq i32 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v16i32(ptr %ptr) nounwind { +; SSE2-LABEL: test_v16i32: +; SSE2: # %bb.0: +; SSE2-NEXT: pushq %rbx +; SSE2-NEXT: movdqa (%rdi), %xmm0 +; SSE2-NEXT: movdqa 16(%rdi), %xmm1 +; SSE2-NEXT: movdqa 32(%rdi), %xmm2 +; SSE2-NEXT: movdqa 48(%rdi), %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1] +; SSE2-NEXT: movd %xmm4, %ecx +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3] +; SSE2-NEXT: movd %xmm4, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %esi +; SSE2-NEXT: andl %eax, %esi +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] +; SSE2-NEXT: movd %xmm0, %edx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %r8d +; SSE2-NEXT: andl %edx, %r8d +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1] +; SSE2-NEXT: movd %xmm0, %edx +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3] +; SSE2-NEXT: movd %xmm0, %r9d +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %r10d +; SSE2-NEXT: andl %r9d, %r10d +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1] +; SSE2-NEXT: movd %xmm0, %r9d +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3] +; SSE2-NEXT: movd %xmm0, %r11d +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,3,3,3] +; SSE2-NEXT: movd %xmm0, %ebx +; SSE2-NEXT: andl %r11d, %ebx +; SSE2-NEXT: andl (%rdi), %ecx +; SSE2-NEXT: andl %esi, %ecx +; SSE2-NEXT: andl 16(%rdi), %eax +; SSE2-NEXT: andl %r8d, %eax +; SSE2-NEXT: andl %ecx, %eax +; SSE2-NEXT: andl 32(%rdi), %edx +; SSE2-NEXT: andl %r10d, %edx +; SSE2-NEXT: andl 48(%rdi), %r9d +; SSE2-NEXT: andl %ebx, %r9d +; SSE2-NEXT: andl %edx, %r9d +; SSE2-NEXT: andl %eax, %r9d +; SSE2-NEXT: cmpl $-1, %r9d +; SSE2-NEXT: sete %al +; SSE2-NEXT: popq %rbx +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v16i32: +; SSE41: # %bb.0: +; SSE41-NEXT: movl 56(%rdi), %eax +; SSE41-NEXT: movl 48(%rdi), %esi +; SSE41-NEXT: movl 40(%rdi), %edx +; SSE41-NEXT: movl 32(%rdi), %r8d +; SSE41-NEXT: movl 24(%rdi), %ecx +; SSE41-NEXT: movl 16(%rdi), %r9d +; SSE41-NEXT: movl (%rdi), %r10d +; SSE41-NEXT: movl 8(%rdi), %r11d +; SSE41-NEXT: andl 4(%rdi), %r10d +; SSE41-NEXT: andl 12(%rdi), %r11d +; SSE41-NEXT: andl %r10d, %r11d +; SSE41-NEXT: andl 20(%rdi), %r9d +; SSE41-NEXT: andl 28(%rdi), %ecx +; SSE41-NEXT: andl %r9d, %ecx +; SSE41-NEXT: andl %r11d, %ecx +; SSE41-NEXT: andl 36(%rdi), %r8d +; SSE41-NEXT: andl 44(%rdi), %edx +; SSE41-NEXT: andl %r8d, %edx +; SSE41-NEXT: andl 52(%rdi), %esi +; SSE41-NEXT: andl 60(%rdi), %eax +; SSE41-NEXT: andl %esi, %eax +; SSE41-NEXT: andl %edx, %eax +; SSE41-NEXT: andl %ecx, %eax +; SSE41-NEXT: cmpl $-1, %eax +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v16i32: +; AVX: # %bb.0: +; AVX-NEXT: movl (%rdi), %esi +; AVX-NEXT: movl 8(%rdi), %r8d +; AVX-NEXT: movl 24(%rdi), %eax +; AVX-NEXT: movl 16(%rdi), %r9d +; AVX-NEXT: movl 40(%rdi), %edx +; AVX-NEXT: movl 32(%rdi), %r10d +; AVX-NEXT: movl 56(%rdi), %ecx +; AVX-NEXT: movl 48(%rdi), %r11d +; AVX-NEXT: andl 4(%rdi), %esi +; AVX-NEXT: andl 12(%rdi), %r8d +; AVX-NEXT: andl %esi, %r8d +; AVX-NEXT: andl 20(%rdi), %r9d +; AVX-NEXT: andl 28(%rdi), %eax +; AVX-NEXT: andl %r9d, %eax +; AVX-NEXT: andl %r8d, %eax +; AVX-NEXT: andl 36(%rdi), %r10d +; AVX-NEXT: andl 44(%rdi), %edx +; AVX-NEXT: andl %r10d, %edx +; AVX-NEXT: andl 52(%rdi), %r11d +; AVX-NEXT: andl 60(%rdi), %ecx +; AVX-NEXT: andl %r11d, %ecx +; AVX-NEXT: andl %edx, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: cmpl $-1, %ecx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <16 x i32>, ptr %ptr + %v0 = extractelement <16 x i32> %vload, i32 0 + %v1 = extractelement <16 x i32> %vload, i32 1 + %v2 = extractelement <16 x i32> %vload, i32 2 + %v3 = extractelement <16 x i32> %vload, i32 3 + %v4 = extractelement <16 x i32> %vload, i32 4 + %v5 = extractelement <16 x i32> %vload, i32 5 + %v6 = extractelement <16 x i32> %vload, i32 6 + %v7 = extractelement <16 x i32> %vload, i32 7 + %v8 = extractelement <16 x i32> %vload, i32 8 + %v9 = extractelement <16 x i32> %vload, i32 9 + %v10 = extractelement <16 x i32> %vload, i32 10 + %v11 = extractelement <16 x i32> %vload, i32 11 + %v12 = extractelement <16 x i32> %vload, i32 12 + %v13 = extractelement <16 x i32> %vload, i32 13 + %v14 = extractelement <16 x i32> %vload, i32 14 + %v15 = extractelement <16 x i32> %vload, i32 15 + %vreduce01 = and i32 %v0, %v1 + %vreduce23 = and i32 %v2, %v3 + %vreduce45 = and i32 %v4, %v5 + %vreduce67 = and i32 %v6, %v7 + %vreduce89 = and i32 %v8, %v9 + %vreduce1011 = and i32 %v10, %v11 + %vreduce1213 = and i32 %v12, %v13 + %vreduce1415 = and i32 %v14, %v15 + %vreduce0123 = and i32 %vreduce01, %vreduce23 + %vreduce4567 = and i32 %vreduce45, %vreduce67 + %vreduce891011 = and i32 %vreduce89, %vreduce1011 + %vreduce12131415 = and i32 %vreduce1213, %vreduce1415 + %vreduce01234567 = and i32 %vreduce0123, %vreduce4567 + %vreduce89101112131415 = and i32 %vreduce891011, %vreduce12131415 + %vreduce = and i32 %vreduce01234567, %vreduce89101112131415 + %vcheck = icmp eq i32 %vreduce, -1 + ret i1 %vcheck +} + +; +; vXi16 +; + +define i1 @test_v2i16(ptr %ptr) nounwind { +; SSE-LABEL: test_v2i16: +; SSE: # %bb.0: +; SSE-NEXT: movl (%rdi), %eax +; SSE-NEXT: movl %eax, %ecx +; SSE-NEXT: shrl $16, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: cmpw $-1, %cx +; SSE-NEXT: sete %al +; SSE-NEXT: retq +; +; AVX-LABEL: test_v2i16: +; AVX: # %bb.0: +; AVX-NEXT: movl (%rdi), %eax +; AVX-NEXT: movl %eax, %ecx +; AVX-NEXT: shrl $16, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: cmpw $-1, %cx +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <2 x i16>, ptr %ptr + %v0 = extractelement <2 x i16> %vload, i32 0 + %v1 = extractelement <2 x i16> %vload, i32 1 + %vreduce = and i16 %v0, %v1 + %vcheck = icmp eq i16 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v4i16(ptr %ptr) nounwind { +; SSE-LABEL: test_v4i16: +; SSE: # %bb.0: +; SSE-NEXT: movq (%rdi), %rax +; SSE-NEXT: movq %rax, %rcx +; SSE-NEXT: movl %eax, %edx +; SSE-NEXT: shrl $16, %edx +; SSE-NEXT: andl %eax, %edx +; SSE-NEXT: shrq $32, %rax +; SSE-NEXT: shrq $48, %rcx +; SSE-NEXT: andl %ecx, %eax +; SSE-NEXT: andl %edx, %eax +; SSE-NEXT: cmpw $-1, %ax +; SSE-NEXT: sete %al +; SSE-NEXT: retq +; +; AVX-LABEL: test_v4i16: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rax +; AVX-NEXT: movq %rax, %rcx +; AVX-NEXT: movl %eax, %edx +; AVX-NEXT: shrl $16, %edx +; AVX-NEXT: andl %eax, %edx +; AVX-NEXT: shrq $32, %rax +; AVX-NEXT: shrq $48, %rcx +; AVX-NEXT: andl %ecx, %eax +; AVX-NEXT: andl %edx, %eax +; AVX-NEXT: cmpw $-1, %ax +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <4 x i16>, ptr %ptr + %v0 = extractelement <4 x i16> %vload, i32 0 + %v1 = extractelement <4 x i16> %vload, i32 1 + %v2 = extractelement <4 x i16> %vload, i32 2 + %v3 = extractelement <4 x i16> %vload, i32 3 + %vreduce01 = and i16 %v0, %v1 + %vreduce23 = and i16 %v2, %v3 + %vreduce = and i16 %vreduce01, %vreduce23 + %vcheck = icmp eq i16 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v8i16(ptr %ptr) nounwind { +; SSE-LABEL: test_v8i16: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rdi), %xmm0 +; SSE-NEXT: movd %xmm0, %eax +; SSE-NEXT: pextrw $1, %xmm0, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: pextrw $2, %xmm0, %eax +; SSE-NEXT: pextrw $3, %xmm0, %edx +; SSE-NEXT: andl %eax, %edx +; SSE-NEXT: andl %ecx, %edx +; SSE-NEXT: pextrw $4, %xmm0, %eax +; SSE-NEXT: pextrw $5, %xmm0, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: pextrw $6, %xmm0, %eax +; SSE-NEXT: pextrw $7, %xmm0, %esi +; SSE-NEXT: andl %eax, %esi +; SSE-NEXT: andl %ecx, %esi +; SSE-NEXT: andl %edx, %esi +; SSE-NEXT: cmpw $-1, %si +; SSE-NEXT: sete %al +; SSE-NEXT: retq +; +; AVX-LABEL: test_v8i16: +; AVX: # %bb.0: +; AVX-NEXT: vmovdqa (%rdi), %xmm0 +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: vpextrw $1, %xmm0, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: vpextrw $2, %xmm0, %eax +; AVX-NEXT: vpextrw $3, %xmm0, %edx +; AVX-NEXT: andl %eax, %edx +; AVX-NEXT: andl %ecx, %edx +; AVX-NEXT: vpextrw $4, %xmm0, %eax +; AVX-NEXT: vpextrw $5, %xmm0, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: vpextrw $6, %xmm0, %eax +; AVX-NEXT: vpextrw $7, %xmm0, %esi +; AVX-NEXT: andl %eax, %esi +; AVX-NEXT: andl %ecx, %esi +; AVX-NEXT: andl %edx, %esi +; AVX-NEXT: cmpw $-1, %si +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <8 x i16>, ptr %ptr + %v0 = extractelement <8 x i16> %vload, i32 0 + %v1 = extractelement <8 x i16> %vload, i32 1 + %v2 = extractelement <8 x i16> %vload, i32 2 + %v3 = extractelement <8 x i16> %vload, i32 3 + %v4 = extractelement <8 x i16> %vload, i32 4 + %v5 = extractelement <8 x i16> %vload, i32 5 + %v6 = extractelement <8 x i16> %vload, i32 6 + %v7 = extractelement <8 x i16> %vload, i32 7 + %vreduce01 = and i16 %v0, %v1 + %vreduce23 = and i16 %v2, %v3 + %vreduce45 = and i16 %v4, %v5 + %vreduce67 = and i16 %v6, %v7 + %vreduce0123 = and i16 %vreduce01, %vreduce23 + %vreduce4567 = and i16 %vreduce45, %vreduce67 + %vreduce = and i16 %vreduce0123, %vreduce4567 + %vcheck = icmp eq i16 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v16i16(ptr %ptr) nounwind { +; SSE-LABEL: test_v16i16: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rdi), %xmm1 +; SSE-NEXT: movdqa 16(%rdi), %xmm0 +; SSE-NEXT: movd %xmm1, %eax +; SSE-NEXT: pextrw $1, %xmm1, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: pextrw $2, %xmm1, %eax +; SSE-NEXT: pextrw $3, %xmm1, %edx +; SSE-NEXT: andl %eax, %edx +; SSE-NEXT: andl %ecx, %edx +; SSE-NEXT: pextrw $4, %xmm1, %eax +; SSE-NEXT: pextrw $5, %xmm1, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: pextrw $6, %xmm1, %eax +; SSE-NEXT: pextrw $7, %xmm1, %esi +; SSE-NEXT: andl %eax, %esi +; SSE-NEXT: andl %ecx, %esi +; SSE-NEXT: andl %edx, %esi +; SSE-NEXT: movd %xmm0, %eax +; SSE-NEXT: pextrw $1, %xmm0, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: pextrw $2, %xmm0, %eax +; SSE-NEXT: pextrw $3, %xmm0, %edx +; SSE-NEXT: andl %eax, %edx +; SSE-NEXT: andl %ecx, %edx +; SSE-NEXT: pextrw $4, %xmm0, %eax +; SSE-NEXT: pextrw $5, %xmm0, %ecx +; SSE-NEXT: andl %eax, %ecx +; SSE-NEXT: pextrw $6, %xmm0, %eax +; SSE-NEXT: pextrw $7, %xmm0, %edi +; SSE-NEXT: andl %eax, %edi +; SSE-NEXT: andl %ecx, %edi +; SSE-NEXT: andl %edx, %edi +; SSE-NEXT: andl %esi, %edi +; SSE-NEXT: cmpw $-1, %di +; SSE-NEXT: sete %al +; SSE-NEXT: retq +; +; AVX1OR2-LABEL: test_v16i16: +; AVX1OR2: # %bb.0: +; AVX1OR2-NEXT: vmovdqa (%rdi), %xmm1 +; AVX1OR2-NEXT: vmovdqa 16(%rdi), %xmm0 +; AVX1OR2-NEXT: vmovd %xmm1, %eax +; AVX1OR2-NEXT: vpextrw $1, %xmm1, %ecx +; AVX1OR2-NEXT: andl %eax, %ecx +; AVX1OR2-NEXT: vpextrw $2, %xmm1, %eax +; AVX1OR2-NEXT: vpextrw $3, %xmm1, %edx +; AVX1OR2-NEXT: andl %eax, %edx +; AVX1OR2-NEXT: andl %ecx, %edx +; AVX1OR2-NEXT: vpextrw $4, %xmm1, %eax +; AVX1OR2-NEXT: vpextrw $5, %xmm1, %ecx +; AVX1OR2-NEXT: andl %eax, %ecx +; AVX1OR2-NEXT: vpextrw $6, %xmm1, %eax +; AVX1OR2-NEXT: vpextrw $7, %xmm1, %esi +; AVX1OR2-NEXT: andl %eax, %esi +; AVX1OR2-NEXT: andl %ecx, %esi +; AVX1OR2-NEXT: andl %edx, %esi +; AVX1OR2-NEXT: vmovd %xmm0, %eax +; AVX1OR2-NEXT: vpextrw $1, %xmm0, %ecx +; AVX1OR2-NEXT: andl %eax, %ecx +; AVX1OR2-NEXT: vpextrw $2, %xmm0, %eax +; AVX1OR2-NEXT: vpextrw $3, %xmm0, %edx +; AVX1OR2-NEXT: andl %eax, %edx +; AVX1OR2-NEXT: andl %ecx, %edx +; AVX1OR2-NEXT: vpextrw $4, %xmm0, %eax +; AVX1OR2-NEXT: vpextrw $5, %xmm0, %ecx +; AVX1OR2-NEXT: andl %eax, %ecx +; AVX1OR2-NEXT: vpextrw $6, %xmm0, %eax +; AVX1OR2-NEXT: vpextrw $7, %xmm0, %edi +; AVX1OR2-NEXT: andl %eax, %edi +; AVX1OR2-NEXT: andl %ecx, %edi +; AVX1OR2-NEXT: andl %edx, %edi +; AVX1OR2-NEXT: andl %esi, %edi +; AVX1OR2-NEXT: cmpw $-1, %di +; AVX1OR2-NEXT: sete %al +; AVX1OR2-NEXT: retq +; +; AVX512F-LABEL: test_v16i16: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqa (%rdi), %xmm1 +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm0 +; AVX512F-NEXT: vmovd %xmm1, %eax +; AVX512F-NEXT: vpextrw $1, %xmm1, %ecx +; AVX512F-NEXT: andl %eax, %ecx +; AVX512F-NEXT: vpextrw $2, %xmm1, %eax +; AVX512F-NEXT: vpextrw $3, %xmm1, %edx +; AVX512F-NEXT: andl %eax, %edx +; AVX512F-NEXT: andl %ecx, %edx +; AVX512F-NEXT: vpextrw $4, %xmm1, %eax +; AVX512F-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512F-NEXT: andl %eax, %ecx +; AVX512F-NEXT: vpextrw $6, %xmm1, %eax +; AVX512F-NEXT: vpextrw $7, %xmm1, %esi +; AVX512F-NEXT: andl %eax, %esi +; AVX512F-NEXT: andl %ecx, %esi +; AVX512F-NEXT: andl %edx, %esi +; AVX512F-NEXT: vmovd %xmm0, %eax +; AVX512F-NEXT: vpextrw $1, %xmm0, %ecx +; AVX512F-NEXT: andl %eax, %ecx +; AVX512F-NEXT: vpextrw $2, %xmm0, %eax +; AVX512F-NEXT: vpextrw $3, %xmm0, %edx +; AVX512F-NEXT: andl %eax, %edx +; AVX512F-NEXT: andl %ecx, %edx +; AVX512F-NEXT: vpextrw $4, %xmm0, %eax +; AVX512F-NEXT: vpextrw $5, %xmm0, %ecx +; AVX512F-NEXT: andl %eax, %ecx +; AVX512F-NEXT: vpextrw $6, %xmm0, %eax +; AVX512F-NEXT: vpextrw $7, %xmm0, %edi +; AVX512F-NEXT: andl %eax, %edi +; AVX512F-NEXT: andl %ecx, %edi +; AVX512F-NEXT: andl %edx, %edi +; AVX512F-NEXT: andl %esi, %edi +; AVX512F-NEXT: cmpw $-1, %di +; AVX512F-NEXT: sete %al +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: test_v16i16: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vmovdqa (%rdi), %xmm1 +; AVX512BW-NEXT: vmovdqa 16(%rdi), %xmm0 +; AVX512BW-NEXT: vmovd %xmm1, %eax +; AVX512BW-NEXT: vpextrw $1, %xmm1, %ecx +; AVX512BW-NEXT: andl %eax, %ecx +; AVX512BW-NEXT: vpextrw $2, %xmm1, %eax +; AVX512BW-NEXT: vpextrw $3, %xmm1, %edx +; AVX512BW-NEXT: andl %eax, %edx +; AVX512BW-NEXT: andl %ecx, %edx +; AVX512BW-NEXT: vpextrw $4, %xmm1, %eax +; AVX512BW-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512BW-NEXT: andl %eax, %ecx +; AVX512BW-NEXT: vpextrw $6, %xmm1, %eax +; AVX512BW-NEXT: vpextrw $7, %xmm1, %esi +; AVX512BW-NEXT: andl %eax, %esi +; AVX512BW-NEXT: andl %ecx, %esi +; AVX512BW-NEXT: andl %edx, %esi +; AVX512BW-NEXT: vmovd %xmm0, %eax +; AVX512BW-NEXT: vpextrw $1, %xmm0, %ecx +; AVX512BW-NEXT: andl %eax, %ecx +; AVX512BW-NEXT: vpextrw $2, %xmm0, %eax +; AVX512BW-NEXT: vpextrw $3, %xmm0, %edx +; AVX512BW-NEXT: andl %eax, %edx +; AVX512BW-NEXT: andl %ecx, %edx +; AVX512BW-NEXT: vpextrw $4, %xmm0, %eax +; AVX512BW-NEXT: vpextrw $5, %xmm0, %ecx +; AVX512BW-NEXT: andl %eax, %ecx +; AVX512BW-NEXT: vpextrw $6, %xmm0, %eax +; AVX512BW-NEXT: vpextrw $7, %xmm0, %edi +; AVX512BW-NEXT: andl %eax, %edi +; AVX512BW-NEXT: andl %ecx, %edi +; AVX512BW-NEXT: andl %edx, %edi +; AVX512BW-NEXT: andl %esi, %edi +; AVX512BW-NEXT: cmpw $-1, %di +; AVX512BW-NEXT: sete %al +; AVX512BW-NEXT: retq +; +; AVX512VL-LABEL: test_v16i16: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512VL-NEXT: vmovd %xmm0, %eax +; AVX512VL-NEXT: vpextrw $1, %xmm0, %ecx +; AVX512VL-NEXT: andl %eax, %ecx +; AVX512VL-NEXT: vpextrw $2, %xmm0, %eax +; AVX512VL-NEXT: vpextrw $3, %xmm0, %edx +; AVX512VL-NEXT: andl %eax, %edx +; AVX512VL-NEXT: andl %ecx, %edx +; AVX512VL-NEXT: vpextrw $4, %xmm0, %eax +; AVX512VL-NEXT: vpextrw $5, %xmm0, %ecx +; AVX512VL-NEXT: andl %eax, %ecx +; AVX512VL-NEXT: vpextrw $6, %xmm0, %eax +; AVX512VL-NEXT: vpextrw $7, %xmm0, %esi +; AVX512VL-NEXT: andl %eax, %esi +; AVX512VL-NEXT: andl %ecx, %esi +; AVX512VL-NEXT: andl %edx, %esi +; AVX512VL-NEXT: vmovd %xmm1, %eax +; AVX512VL-NEXT: vpextrw $1, %xmm1, %ecx +; AVX512VL-NEXT: andl %eax, %ecx +; AVX512VL-NEXT: vpextrw $2, %xmm1, %eax +; AVX512VL-NEXT: vpextrw $3, %xmm1, %edx +; AVX512VL-NEXT: andl %eax, %edx +; AVX512VL-NEXT: andl %ecx, %edx +; AVX512VL-NEXT: vpextrw $4, %xmm1, %eax +; AVX512VL-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512VL-NEXT: andl %eax, %ecx +; AVX512VL-NEXT: vpextrw $6, %xmm1, %eax +; AVX512VL-NEXT: vpextrw $7, %xmm1, %edi +; AVX512VL-NEXT: andl %eax, %edi +; AVX512VL-NEXT: andl %ecx, %edi +; AVX512VL-NEXT: andl %edx, %edi +; AVX512VL-NEXT: andl %esi, %edi +; AVX512VL-NEXT: cmpw $-1, %di +; AVX512VL-NEXT: sete %al +; AVX512VL-NEXT: retq + %vload = load <16 x i16>, ptr %ptr + %v0 = extractelement <16 x i16> %vload, i32 0 + %v1 = extractelement <16 x i16> %vload, i32 1 + %v2 = extractelement <16 x i16> %vload, i32 2 + %v3 = extractelement <16 x i16> %vload, i32 3 + %v4 = extractelement <16 x i16> %vload, i32 4 + %v5 = extractelement <16 x i16> %vload, i32 5 + %v6 = extractelement <16 x i16> %vload, i32 6 + %v7 = extractelement <16 x i16> %vload, i32 7 + %v8 = extractelement <16 x i16> %vload, i32 8 + %v9 = extractelement <16 x i16> %vload, i32 9 + %v10 = extractelement <16 x i16> %vload, i32 10 + %v11 = extractelement <16 x i16> %vload, i32 11 + %v12 = extractelement <16 x i16> %vload, i32 12 + %v13 = extractelement <16 x i16> %vload, i32 13 + %v14 = extractelement <16 x i16> %vload, i32 14 + %v15 = extractelement <16 x i16> %vload, i32 15 + %vreduce01 = and i16 %v0, %v1 + %vreduce23 = and i16 %v2, %v3 + %vreduce45 = and i16 %v4, %v5 + %vreduce67 = and i16 %v6, %v7 + %vreduce89 = and i16 %v8, %v9 + %vreduce1011 = and i16 %v10, %v11 + %vreduce1213 = and i16 %v12, %v13 + %vreduce1415 = and i16 %v14, %v15 + %vreduce0123 = and i16 %vreduce01, %vreduce23 + %vreduce4567 = and i16 %vreduce45, %vreduce67 + %vreduce891011 = and i16 %vreduce89, %vreduce1011 + %vreduce12131415 = and i16 %vreduce1213, %vreduce1415 + %vreduce01234567 = and i16 %vreduce0123, %vreduce4567 + %vreduce89101112131415 = and i16 %vreduce891011, %vreduce12131415 + %vreduce = and i16 %vreduce01234567, %vreduce89101112131415 + %vcheck = icmp eq i16 %vreduce, -1 + ret i1 %vcheck +} + +; +; vXi8 +; + +define i1 @test_v2i8(ptr %ptr) nounwind { +; SSE2-LABEL: test_v2i8: +; SSE2: # %bb.0: +; SSE2-NEXT: movzwl (%rdi), %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %al +; SSE2-NEXT: cmpb $-1, %al +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v2i8: +; SSE41: # %bb.0: +; SSE41-NEXT: movzwl (%rdi), %eax +; SSE41-NEXT: movl %eax, %ecx +; SSE41-NEXT: shrl $8, %ecx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: cmpb $-1, %cl +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v2i8: +; AVX: # %bb.0: +; AVX-NEXT: movzwl (%rdi), %eax +; AVX-NEXT: movl %eax, %ecx +; AVX-NEXT: shrl $8, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: cmpb $-1, %cl +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <2 x i8>, ptr %ptr + %v0 = extractelement <2 x i8> %vload, i32 0 + %v1 = extractelement <2 x i8> %vload, i32 1 + %vreduce = and i8 %v0, %v1 + %vcheck = icmp eq i8 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v4i8(ptr %ptr) nounwind { +; SSE2-LABEL: test_v4i8: +; SSE2: # %bb.0: +; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %al +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %cl +; SSE2-NEXT: andb %al, %cl +; SSE2-NEXT: cmpb $-1, %cl +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v4i8: +; SSE41: # %bb.0: +; SSE41-NEXT: movl (%rdi), %eax +; SSE41-NEXT: movl %eax, %ecx +; SSE41-NEXT: shrl $8, %ecx +; SSE41-NEXT: movl %eax, %edx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: shrl $16, %eax +; SSE41-NEXT: shrl $24, %edx +; SSE41-NEXT: andl %eax, %edx +; SSE41-NEXT: andl %edx, %ecx +; SSE41-NEXT: cmpb $-1, %cl +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v4i8: +; AVX: # %bb.0: +; AVX-NEXT: movl (%rdi), %eax +; AVX-NEXT: movl %eax, %ecx +; AVX-NEXT: shrl $8, %ecx +; AVX-NEXT: movl %eax, %edx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: shrl $16, %eax +; AVX-NEXT: shrl $24, %edx +; AVX-NEXT: andl %eax, %edx +; AVX-NEXT: andl %edx, %ecx +; AVX-NEXT: cmpb $-1, %cl +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <4 x i8>, ptr %ptr + %v0 = extractelement <4 x i8> %vload, i32 0 + %v1 = extractelement <4 x i8> %vload, i32 1 + %v2 = extractelement <4 x i8> %vload, i32 2 + %v3 = extractelement <4 x i8> %vload, i32 3 + %vreduce01 = and i8 %v0, %v1 + %vreduce23 = and i8 %v2, %v3 + %vreduce = and i8 %vreduce01, %vreduce23 + %vcheck = icmp eq i8 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v8i8(ptr %ptr) nounwind { +; SSE2-LABEL: test_v8i8: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %al +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %cl +; SSE2-NEXT: andb %al, %cl +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %dl +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %sil +; SSE2-NEXT: andb %dl, %sil +; SSE2-NEXT: andb %cl, %sil +; SSE2-NEXT: cmpb $-1, %sil +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v8i8: +; SSE41: # %bb.0: +; SSE41-NEXT: movq (%rdi), %rax +; SSE41-NEXT: movq %rax, %rcx +; SSE41-NEXT: shrq $32, %rcx +; SSE41-NEXT: movq %rax, %rdx +; SSE41-NEXT: shrq $40, %rdx +; SSE41-NEXT: movq %rax, %rsi +; SSE41-NEXT: shrq $48, %rsi +; SSE41-NEXT: movq %rax, %rdi +; SSE41-NEXT: shrq $56, %rdi +; SSE41-NEXT: movl %eax, %r8d +; SSE41-NEXT: shrl $8, %r8d +; SSE41-NEXT: andl %eax, %r8d +; SSE41-NEXT: movl %eax, %r9d +; SSE41-NEXT: shrl $24, %r9d +; SSE41-NEXT: shrl $16, %eax +; SSE41-NEXT: andl %r9d, %eax +; SSE41-NEXT: andl %r8d, %eax +; SSE41-NEXT: andl %edx, %ecx +; SSE41-NEXT: andl %edi, %esi +; SSE41-NEXT: andl %ecx, %esi +; SSE41-NEXT: andl %eax, %esi +; SSE41-NEXT: cmpb $-1, %sil +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v8i8: +; AVX: # %bb.0: +; AVX-NEXT: movq (%rdi), %rax +; AVX-NEXT: movq %rax, %rcx +; AVX-NEXT: shrq $32, %rcx +; AVX-NEXT: movq %rax, %rdx +; AVX-NEXT: shrq $40, %rdx +; AVX-NEXT: movq %rax, %rsi +; AVX-NEXT: shrq $48, %rsi +; AVX-NEXT: movq %rax, %rdi +; AVX-NEXT: shrq $56, %rdi +; AVX-NEXT: movl %eax, %r8d +; AVX-NEXT: shrl $8, %r8d +; AVX-NEXT: andl %eax, %r8d +; AVX-NEXT: movl %eax, %r9d +; AVX-NEXT: shrl $24, %r9d +; AVX-NEXT: shrl $16, %eax +; AVX-NEXT: andl %r9d, %eax +; AVX-NEXT: andl %r8d, %eax +; AVX-NEXT: andl %edx, %ecx +; AVX-NEXT: andl %edi, %esi +; AVX-NEXT: andl %ecx, %esi +; AVX-NEXT: andl %eax, %esi +; AVX-NEXT: cmpb $-1, %sil +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <8 x i8>, ptr %ptr + %v0 = extractelement <8 x i8> %vload, i32 0 + %v1 = extractelement <8 x i8> %vload, i32 1 + %v2 = extractelement <8 x i8> %vload, i32 2 + %v3 = extractelement <8 x i8> %vload, i32 3 + %v4 = extractelement <8 x i8> %vload, i32 4 + %v5 = extractelement <8 x i8> %vload, i32 5 + %v6 = extractelement <8 x i8> %vload, i32 6 + %v7 = extractelement <8 x i8> %vload, i32 7 + %vreduce01 = and i8 %v0, %v1 + %vreduce23 = and i8 %v2, %v3 + %vreduce45 = and i8 %v4, %v5 + %vreduce67 = and i8 %v6, %v7 + %vreduce0123 = and i8 %vreduce01, %vreduce23 + %vreduce4567 = and i8 %vreduce45, %vreduce67 + %vreduce = and i8 %vreduce0123, %vreduce4567 + %vcheck = icmp eq i8 %vreduce, -1 + ret i1 %vcheck +} + +define i1 @test_v16i8(ptr %ptr) nounwind { +; SSE2-LABEL: test_v16i8: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps (%rdi), %xmm0 +; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r10d +; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %dl +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %sil +; SSE2-NEXT: andb %dl, %sil +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %dil +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %al +; SSE2-NEXT: andb %dil, %al +; SSE2-NEXT: andb %sil, %al +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %r8b +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %r9b +; SSE2-NEXT: andb %r8b, %r9b +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %r10b +; SSE2-NEXT: andb -{{[0-9]+}}(%rsp), %cl +; SSE2-NEXT: andb %r10b, %cl +; SSE2-NEXT: andb %r9b, %cl +; SSE2-NEXT: andb %al, %cl +; SSE2-NEXT: cmpb $-1, %cl +; SSE2-NEXT: sete %al +; SSE2-NEXT: retq +; +; SSE41-LABEL: test_v16i8: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa (%rdi), %xmm0 +; SSE41-NEXT: movd %xmm0, %eax +; SSE41-NEXT: pextrb $1, %xmm0, %ecx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: pextrb $2, %xmm0, %eax +; SSE41-NEXT: pextrb $3, %xmm0, %edx +; SSE41-NEXT: andl %eax, %edx +; SSE41-NEXT: andl %ecx, %edx +; SSE41-NEXT: pextrb $4, %xmm0, %eax +; SSE41-NEXT: pextrb $5, %xmm0, %ecx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: pextrb $6, %xmm0, %eax +; SSE41-NEXT: pextrb $7, %xmm0, %esi +; SSE41-NEXT: andl %eax, %esi +; SSE41-NEXT: andl %ecx, %esi +; SSE41-NEXT: andl %edx, %esi +; SSE41-NEXT: pextrb $8, %xmm0, %eax +; SSE41-NEXT: pextrb $9, %xmm0, %ecx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: pextrb $10, %xmm0, %eax +; SSE41-NEXT: pextrb $11, %xmm0, %edx +; SSE41-NEXT: andl %eax, %edx +; SSE41-NEXT: andl %ecx, %edx +; SSE41-NEXT: pextrb $12, %xmm0, %eax +; SSE41-NEXT: pextrb $13, %xmm0, %ecx +; SSE41-NEXT: andl %eax, %ecx +; SSE41-NEXT: pextrb $14, %xmm0, %eax +; SSE41-NEXT: pextrb $15, %xmm0, %edi +; SSE41-NEXT: andl %eax, %edi +; SSE41-NEXT: andl %ecx, %edi +; SSE41-NEXT: andl %edx, %edi +; SSE41-NEXT: andl %esi, %edi +; SSE41-NEXT: cmpb $-1, %dil +; SSE41-NEXT: sete %al +; SSE41-NEXT: retq +; +; AVX-LABEL: test_v16i8: +; AVX: # %bb.0: +; AVX-NEXT: vmovdqa (%rdi), %xmm0 +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: vpextrb $1, %xmm0, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: vpextrb $2, %xmm0, %eax +; AVX-NEXT: vpextrb $3, %xmm0, %edx +; AVX-NEXT: andl %eax, %edx +; AVX-NEXT: andl %ecx, %edx +; AVX-NEXT: vpextrb $4, %xmm0, %eax +; AVX-NEXT: vpextrb $5, %xmm0, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: vpextrb $6, %xmm0, %eax +; AVX-NEXT: vpextrb $7, %xmm0, %esi +; AVX-NEXT: andl %eax, %esi +; AVX-NEXT: andl %ecx, %esi +; AVX-NEXT: andl %edx, %esi +; AVX-NEXT: vpextrb $8, %xmm0, %eax +; AVX-NEXT: vpextrb $9, %xmm0, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: vpextrb $10, %xmm0, %eax +; AVX-NEXT: vpextrb $11, %xmm0, %edx +; AVX-NEXT: andl %eax, %edx +; AVX-NEXT: andl %ecx, %edx +; AVX-NEXT: vpextrb $12, %xmm0, %eax +; AVX-NEXT: vpextrb $13, %xmm0, %ecx +; AVX-NEXT: andl %eax, %ecx +; AVX-NEXT: vpextrb $14, %xmm0, %eax +; AVX-NEXT: vpextrb $15, %xmm0, %edi +; AVX-NEXT: andl %eax, %edi +; AVX-NEXT: andl %ecx, %edi +; AVX-NEXT: andl %edx, %edi +; AVX-NEXT: andl %esi, %edi +; AVX-NEXT: cmpb $-1, %dil +; AVX-NEXT: sete %al +; AVX-NEXT: retq + %vload = load <16 x i8>, ptr %ptr + %v0 = extractelement <16 x i8> %vload, i32 0 + %v1 = extractelement <16 x i8> %vload, i32 1 + %v2 = extractelement <16 x i8> %vload, i32 2 + %v3 = extractelement <16 x i8> %vload, i32 3 + %v4 = extractelement <16 x i8> %vload, i32 4 + %v5 = extractelement <16 x i8> %vload, i32 5 + %v6 = extractelement <16 x i8> %vload, i32 6 + %v7 = extractelement <16 x i8> %vload, i32 7 + %v8 = extractelement <16 x i8> %vload, i32 8 + %v9 = extractelement <16 x i8> %vload, i32 9 + %v10 = extractelement <16 x i8> %vload, i32 10 + %v11 = extractelement <16 x i8> %vload, i32 11 + %v12 = extractelement <16 x i8> %vload, i32 12 + %v13 = extractelement <16 x i8> %vload, i32 13 + %v14 = extractelement <16 x i8> %vload, i32 14 + %v15 = extractelement <16 x i8> %vload, i32 15 + %vreduce01 = and i8 %v0, %v1 + %vreduce23 = and i8 %v2, %v3 + %vreduce45 = and i8 %v4, %v5 + %vreduce67 = and i8 %v6, %v7 + %vreduce89 = and i8 %v8, %v9 + %vreduce1011 = and i8 %v10, %v11 + %vreduce1213 = and i8 %v12, %v13 + %vreduce1415 = and i8 %v14, %v15 + %vreduce0123 = and i8 %vreduce01, %vreduce23 + %vreduce4567 = and i8 %vreduce45, %vreduce67 + %vreduce891011 = and i8 %vreduce89, %vreduce1011 + %vreduce12131415 = and i8 %vreduce1213, %vreduce1415 + %vreduce01234567 = and i8 %vreduce0123, %vreduce4567 + %vreduce89101112131415 = and i8 %vreduce891011, %vreduce12131415 + %vreduce = and i8 %vreduce01234567, %vreduce89101112131415 + %vcheck = icmp eq i8 %vreduce, -1 + ret i1 %vcheck +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX1: {{.*}} +; AVX2: {{.*}} +; AVX512: {{.*}}