From: Michael Meissner Date: Thu, 4 Feb 2016 00:39:34 +0000 (+0000) Subject: re PR target/69461 (ICE in lra_set_insn_recog_data, at lra.c:964) X-Git-Tag: upstream/12.2.0~49001 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5a01e0c7618b26569aee56a9443b71d501c69a50;p=platform%2Fupstream%2Fgcc.git re PR target/69461 (ICE in lra_set_insn_recog_data, at lra.c:964) 2016-02-03 Michael Meissner Vladimir Makarov PR target/69461 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Fix thinko in validating fused toc addresses. Co-Authored-By: Vladimir Makarov From-SVN: r233120 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 142e7a4..f379bc4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-02-03 Michael Meissner + Vladimir Makarov + + PR target/69461 + * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Fix thinko + in validating fused toc addresses. + 2016-02-03 Jakub Jelinek PR c/69627 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6f382cb..c7e0634 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -8399,7 +8399,8 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) && legitimate_constant_pool_address_p (x, mode, reg_ok_strict || lra_in_progress)) return 1; - if (reg_offset_p && reg_addr[mode].fused_toc && toc_fusion_mem_wrapped (x, mode)) + if (reg_offset_p && reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC + && XINT (x, 1) == UNSPEC_FUSION_ADDIS) return 1; /* For TImode, if we have load/store quad and TImode in VSX registers, only allow register indirect addresses. This will allow the values to go in