From: Dinh Nguyen <dinguyen@kernel.org>
Date: Wed, 25 Jan 2017 16:01:28 +0000 (-0600)
Subject: ARM: dts: watchdog0 cannot reliably trigger reset
X-Git-Tag: v4.11-rc1~87^2~5^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=59d94d2ed45d598211feb52566e6a806d17f8a3f;p=platform%2Fkernel%2Flinux-exynos.git

ARM: dts: watchdog0 cannot reliably trigger reset

On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger
a reset to the CPU. The workaround would be to use watchdog1 instead.

Also for watchdog1, there is a dependency on the bootloader to enable the
boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This
corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the
control register in the clock manager module of Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 4c99c99..c57e6ce 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -160,6 +160,6 @@
 	status = "okay";
 };
 
-&watchdog0 {
+&watchdog1 {
 	status = "okay";
 };