From: Francisco Jerez Date: Fri, 9 Dec 2016 02:00:17 +0000 (-0800) Subject: i965/gen6+: Invalidate constant cache on brw_emit_mi_flush(). X-Git-Tag: upstream/17.1.0~3930 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=591e14ec08b13e8d50636feb1afa578257175b9d;p=platform%2Fupstream%2Fmesa.git i965/gen6+: Invalidate constant cache on brw_emit_mi_flush(). In order to make sure that the constant cache is coherent with previous rendering when we start using it for pull constant loads. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index dd426bf..b8f7406 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -351,6 +351,7 @@ brw_emit_mi_flush(struct brw_context *brw) int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; if (brw->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | + PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |