From: Stephen Boyd Date: Fri, 14 Dec 2018 21:34:47 +0000 (-0800) Subject: Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and... X-Git-Tag: v5.4-rc1~1882^2~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=58c05c823b8347daf03a8448e38318820fad6645;p=platform%2Fkernel%2Flinux-rpi.git Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next - NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM --- 58c05c823b8347daf03a8448e38318820fad6645 diff --cc drivers/clk/Kconfig index 2dc12bf,81cdb4e,81cdb4e,81cdb4e,1dbfcc2,5c1e0c7..e5b2fe8 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@@@@@@ -293,7 -286,7 -286,7 -286,7 -286,8 -286,8 +293,9 @@@@@@@ config COMMON_CLK_BD718X source "drivers/clk/actions/Kconfig" source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" +++++ source "drivers/clk/imx/Kconfig" source "drivers/clk/imgtec/Kconfig" ++++ +source "drivers/clk/imx/Kconfig" source "drivers/clk/ingenic/Kconfig" source "drivers/clk/keystone/Kconfig" source "drivers/clk/mediatek/Kconfig" diff --cc drivers/clk/imx/Kconfig index 0000000,0000000,0000000,0000000,a509a8f,98ede6a..4aae31a mode 000000,000000,000000,000000,100644,100644..100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@@@@@@ -1,0 -1,0 -1,0 -1,0 -1,16 -1,5 +1,22 @@@@@@@ ++++ +# SPDX-License-Identifier: GPL-2.0 ++++ +# common clock support for NXP i.MX SoC family. ++++ +config MXC_CLK ++++ + bool ++++ + def_bool ARCH_MXC ++++ + ++++ +config MXC_CLK_SCU ++++ + bool ++++ + depends on IMX_SCU ++++ + +++++ config CLK_IMX8MQ +++++ bool "IMX8MQ CCM Clock Driver" +++++ depends on ARCH_MXC && ARM64 +++++ help +++++ Build the driver for i.MX8MQ CCM Clock Driver ++++++ ++++ +config CLK_IMX8QXP ++++ + bool "IMX8QXP SCU Clock" ++++ + depends on ARCH_MXC && IMX_SCU && ARM64 ++++ + select MXC_CLK_SCU ++++ + help ++++ + Build the driver for IMX8QXP SCU based clocks. diff --cc drivers/clk/imx/Makefile index 8c3baa7,615b413,8c3baa7,8c3baa7,953a92a,c4a1378..73119fb --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@@@@@@ -1,17 -1,21 -1,17 -1,17 -1,23 -1,22 +1,31 @@@@@@@ # SPDX-License-Identifier: GPL-2.0 ---- -obj-y += \ ++++ +obj-$(CONFIG_MXC_CLK) += \ clk.o \ clk-busy.o \ +++++ clk-composite-8m.o \ clk-cpu.o \ + ++++ clk-composite-7ulp.o \ + ++++ clk-divider-gate.o \ clk-fixup-div.o \ clk-fixup-mux.o \ +++++ clk-frac-pll.o \ clk-gate-exclusive.o \ clk-gate2.o \ ++++++ clk-pfd.o \ ++++++ clk-pfdv2.o \ clk-pllv1.o \ clk-pllv2.o \ clk-pllv3.o \ - --- clk-pfd.o - clk-pfd.o \ + ++++ clk-pllv4.o \ - clk-pfd.o \ - clk-pfdv2.o +++++ clk-sccg-pll.o ++++ ++++ +obj-$(CONFIG_MXC_CLK_SCU) += \ ++++ + clk-scu.o \ ++++ + clk-lpcg-scu.o ++++ + +++++ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o ++++ +obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o @@@@@@@ -26,4 -30,5 -26,4 -26,4 -32,4 -31,5 +40,5 @@@@@@@ obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sl obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o -obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o + ++++obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o diff --cc drivers/clk/imx/clk.h index 5895e223,a34b93e,5895e223,5895e223,5895e223,34357ca..028312d --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@@@@@@ -198,8 -250,9 -198,8 -198,8 -198,8 -228,17 +280,18 @@@@@@@ static inline struct clk *imx_clk_gate4 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); } +++++ static inline struct clk *imx_clk_gate4_flags(const char *name, +++++ const char *parent, void __iomem *reg, u8 shift, +++++ unsigned long flags) +++++ { +++++ return clk_register_gate2(NULL, name, parent, +++++ flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, +++++ reg, shift, 0x3, 0, &imx_ccm_lock, NULL); +++++ } +++++ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, - ---- u8 shift, u8 width, const char **parents, int num_parents) + ++++ u8 shift, u8 width, const char * const *parents, + ++++ int num_parents) { return clk_register_mux(NULL, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT, reg, shift, @@@@@@@ -223,8 -289,24 -223,8 -223,8 -223,8 -262,33 +328,49 @@@@@@@ static inline struct clk *imx_clk_mux_f &imx_ccm_lock); } +++++ static inline struct clk *imx_clk_mux2_flags(const char *name, +++++ void __iomem *reg, u8 shift, u8 width, const char **parents, +++++ int num_parents, unsigned long flags) +++++ { +++++ return clk_register_mux(NULL, name, parents, num_parents, +++++ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, +++++ reg, shift, width, 0, &imx_ccm_lock); +++++ } +++++ + ++++static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, + ++++ void __iomem *reg, u8 shift, + ++++ u8 width, + ++++ const char * const *parents, + ++++ int num_parents, + ++++ unsigned long flags) + ++++{ + ++++ return clk_hw_register_mux(NULL, name, parents, num_parents, + ++++ flags | CLK_SET_RATE_NO_REPARENT, + ++++ reg, shift, width, 0, &imx_ccm_lock); + ++++} + ++++ struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +++++ struct clk *imx8m_clk_composite_flags(const char *name, +++++ const char **parent_names, +++++ int num_parents, void __iomem *reg, +++++ unsigned long flags); +++++ +++++ #define __imx8m_clk_composite(name, parent_names, reg, flags) \ +++++ imx8m_clk_composite_flags(name, parent_names, \ +++++ ARRAY_SIZE(parent_names), reg, \ +++++ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) +++++ +++++ #define imx8m_clk_composite(name, parent_names, reg) \ +++++ __imx8m_clk_composite(name, parent_names, reg, 0) +++++ +++++ #define imx8m_clk_composite_critical(name, parent_names, reg) \ +++++ __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) +++++ + ++++struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, + ++++ unsigned long flags, void __iomem *reg, u8 shift, u8 width, + ++++ u8 clk_divider_flags, const struct clk_div_table *table, + ++++ spinlock_t *lock); #endif