From: Jinsong Ji Date: Tue, 19 Feb 2019 21:25:13 +0000 (+0000) Subject: PowerPC: Fix typos in comments X-Git-Tag: llvmorg-10-init~11665 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=58bab8e690b5990fd002e2749aa8846fcc3b5bdb;p=platform%2Fupstream%2Fllvm.git PowerPC: Fix typos in comments llvm-svn: 354382 --- diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td index c4c1098..4b49d27 100644 --- a/llvm/lib/Target/PowerPC/P9InstrResources.td +++ b/llvm/lib/Target/PowerPC/P9InstrResources.td @@ -84,7 +84,7 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, )>; // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a -// slingle slice. However, since it is Restricted it requires all 3 dispatches +// single slice. However, since it is Restricted it requires all 3 dispatches // (DISP) for that superslice. def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C], (instrs @@ -170,7 +170,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], )>; // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a -// slingle slice. However, since it is Restricted it requires all 3 dispatches +// single slice. However, since it is Restricted it requires all 3 dispatches // (DISP) for that superslice. def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C], (instrs