From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 22 Jul 2023 13:30:22 +0000 (+0000)
Subject: rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support
X-Git-Tag: v2023.10~65^2~6
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=583a82d5e2702f2c8aadcd75d416d6e45dd5188a;p=platform%2Fkernel%2Fu-boot.git

rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support

Add dummy support for the CLK_PCIEPHY2_REF clock.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 6bdd96f..0df82f5 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
 		break;
 	case CLK_PCIEPHY0_REF:
 	case CLK_PCIEPHY1_REF:
+	case CLK_PCIEPHY2_REF:
 		return 0;
 	default:
 		return -ENOENT;