From: Timur Kristóf <timur.kristof@gmail.com>
Date: Mon, 22 Feb 2021 19:18:08 +0000 (+0100)
Subject: aco: Implement new Geometry Shader intrinsics.
X-Git-Tag: upstream/21.2.3~6362
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=582229585b6625ecc62ed07ac43481e9f3a5d2b3;p=platform%2Fupstream%2Fmesa.git

aco: Implement new Geometry Shader intrinsics.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
---

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 6266431..a015699 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -8175,6 +8175,9 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
       if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) {
          bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.vs_rel_patch_id));
          break;
+      } else if (ctx->stage.hw == HWStage::GS || ctx->stage.hw == HWStage::NGG) {
+         bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), thread_id_in_threadgroup(ctx));
+         break;
       }
 
       Temp id = emit_mbcnt(ctx, bld.tmp(v1));
@@ -8787,6 +8790,21 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
       bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.tess_offchip_offset));
       break;
    }
+   case nir_intrinsic_load_ring_esgs_amd: {
+      unsigned ring = ctx->stage.hw == HWStage::ES ? RING_ESGS_VS : RING_ESGS_GS;
+      bld.smem(aco_opcode::s_load_dwordx4, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
+               ctx->program->private_segment_buffer, Operand(ring * 16u));
+      break;
+   }
+   case nir_intrinsic_load_ring_es2gs_offset_amd: {
+      bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.es2gs_offset));
+      break;
+   }
+   case nir_intrinsic_load_gs_vertex_offset_amd: {
+      unsigned b = nir_intrinsic_base(instr);
+      bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.gs_vtx_offset[b]));
+      break;
+   }
    default:
       isel_err(&instr->instr, "Unimplemented intrinsic instr");
       abort();
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index c721915..0cbbd9d 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -782,6 +782,8 @@ void init_context(isel_context *ctx, nir_shader *shader)
                   case nir_intrinsic_load_ring_tess_factors_offset_amd:
                   case nir_intrinsic_load_ring_tess_offchip_amd:
                   case nir_intrinsic_load_ring_tess_offchip_offset_amd:
+                  case nir_intrinsic_load_ring_esgs_amd:
+                  case nir_intrinsic_load_ring_es2gs_offset_amd:
                      type = RegType::sgpr;
                      break;
                   case nir_intrinsic_load_sample_id:
@@ -858,6 +860,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
                   case nir_intrinsic_load_primitive_id:
                   case nir_intrinsic_load_buffer_amd:
                   case nir_intrinsic_load_tess_rel_patch_id_amd:
+                  case nir_intrinsic_load_gs_vertex_offset_amd:
                      type = RegType::vgpr;
                      break;
                   case nir_intrinsic_shuffle: