From: Weijie Gao <weijie.gao@mediatek.com>
Date: Thu, 11 Jul 2019 06:26:24 +0000 (+0800)
Subject: arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi
X-Git-Tag: v2019.10-rc1~24^2~6
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=58067b0de1e5d8a07ccb8c3a5497beaa0e043c6b;p=platform%2Fkernel%2Fu-boot.git

arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi

The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.

This patch reverses these two clocks to solve this issue.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index c87115e..ecbd29d 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -82,8 +82,8 @@
 		compatible = "mediatek,timer";
 		reg = <0x10004000 0x80>;
 		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&topckgen CLK_TOP_10M_SEL>,
-			 <&topckgen CLK_TOP_CLKXTAL_D4>;
+		clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
+			 <&topckgen CLK_TOP_10M_SEL>;
 		clock-names = "mux", "src";
 		u-boot,dm-pre-reloc;
 	};