From: Richard Sandiford <richard.sandiford@linaro.org>
Date: Tue, 8 May 2018 11:42:15 +0000 (+0000)
Subject: Move C++ SVE tests to g++.target/aarch64/sve
X-Git-Tag: upstream/12.2.0~31969
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=57cfbfbab8ec2a2ca4fb060bf95e0d03a8df57f2;p=platform%2Fupstream%2Fgcc.git

Move C++ SVE tests to g++.target/aarch64/sve

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
	* g++.dg/other/sve_const_pred_1.C: Rename to...
	* g++.target/aarch64/sve/const_pred_1.C: ...this.  Remove aarch64
	target selectors and explicit -march options.
	* g++.dg/other/sve_const_pred_2.C: Rename to...
	* g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise.
	* g++.dg/other/sve_const_pred_3.C: Rename to...
	* g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise.
	* g++.dg/other/sve_const_pred_4.C: Rename to...
	* g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise.
	* g++.dg/other/sve_tls_2.C: Rename to...
	* g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise.
	* g++.dg/other/sve_vcond_1.C: Rename to...
	* g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise.
	* g++.dg/other/sve_vcond_1_run.C: Rename to...
	* g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise.

From-SVN: r260038
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5393aab..2628d55 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,23 @@
 2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>
 
+	* g++.dg/other/sve_const_pred_1.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_1.C: ...this.  Remove aarch64
+	target selectors and explicit -march options.
+	* g++.dg/other/sve_const_pred_2.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise.
+	* g++.dg/other/sve_const_pred_3.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise.
+	* g++.dg/other/sve_const_pred_4.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise.
+	* g++.dg/other/sve_tls_2.C: Rename to...
+	* g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise.
+	* g++.dg/other/sve_vcond_1.C: Rename to...
+	* g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise.
+	* g++.dg/other/sve_vcond_1_run.C: Rename to...
+	* g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise.
+
+2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
 	PR testsuite/85586
 	* gcc.dg/vect/pr85586.c: Restrict LOOP VECTORIZED test to
 	!vect_no_align.
diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_1.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C
similarity index 78%
rename from gcc/testsuite/g++.dg/other/sve_const_pred_1.C
rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C
index cc124c0..25b7663 100644
--- a/gcc/testsuite/g++.dg/other/sve_const_pred_1.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C
@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_2.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C
similarity index 75%
rename from gcc/testsuite/g++.dg/other/sve_const_pred_2.C
rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C
index e3bce39..4c781ca 100644
--- a/gcc/testsuite/g++.dg/other/sve_const_pred_2.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C
@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_3.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C
similarity index 73%
rename from gcc/testsuite/g++.dg/other/sve_const_pred_3.C
rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C
index 9e75f39..6196ee0 100644
--- a/gcc/testsuite/g++.dg/other/sve_const_pred_3.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C
@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_4.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C
similarity index 72%
rename from gcc/testsuite/g++.dg/other/sve_const_pred_4.C
rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C
index 04a1351..2bdf67fd 100644
--- a/gcc/testsuite/g++.dg/other/sve_const_pred_4.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C
@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/g++.dg/other/sve_tls_2.C b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C
similarity index 85%
rename from gcc/testsuite/g++.dg/other/sve_tls_2.C
rename to gcc/testsuite/g++.target/aarch64/sve/tls_2.C
index ed46893..9267f1e 100644
--- a/gcc/testsuite/g++.dg/other/sve_tls_2.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C
@@ -1,6 +1,6 @@
-/* { dg-do compile { target aarch64*-*-* } } */
+/* { dg-do compile } */
 /* { dg-require-effective-target tls } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -fPIC -msve-vector-bits=256" } */
+/* { dg-options "-O2 -fPIC -msve-vector-bits=256" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C
similarity index 99%
rename from gcc/testsuite/g++.dg/other/sve_vcond_1.C
rename to gcc/testsuite/g++.target/aarch64/sve/vcond_1.C
index c1ad0b9..2a80d21 100644
--- a/gcc/testsuite/g++.dg/other/sve_vcond_1.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */
-/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32)));
 typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32)));
diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C
similarity index 88%
rename from gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
rename to gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C
index b542356..d01745e 100644
--- a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C
@@ -1,6 +1,6 @@
 /* { dg-do run { target aarch64_sve_hw } } */
-/* { dg-options "-O -march=armv8.2-a+sve" } */
-/* { dg-options "-O -march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64_sve256_hw } } */
+/* { dg-options "-O" } */
+/* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
 
 #include "sve_vcond_1.c"