From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 11 Oct 2022 17:41:09 +0000 (-0700)
Subject: AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs
X-Git-Tag: upstream/17.0.6~30757
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=575eed3dace3c9c741cfc47be02ea1dee4b0402b;p=platform%2Fupstream%2Fllvm.git

AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs

If inline asm has a VGPR def, it must have come from a VGPR write
somewhere inside the asm. This should be further extended to all
read after write hazards.
---

diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 9f504f6..fb300e8 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1961,7 +1961,7 @@ int GCNHazardRecognizer::checkMAIHazards908(MachineInstr *MI) {
   unsigned Opc = MI->getOpcode();
 
   auto IsVALUFn = [](const MachineInstr &MI) {
-    return SIInstrInfo::isVALU(MI);
+    return SIInstrInfo::isVALU(MI) || MI.isInlineAsm();
   };
 
   if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write
diff --git a/llvm/test/CodeGen/AMDGPU/mai-hazards.mir b/llvm/test/CodeGen/AMDGPU/mai-hazards.mir
index 370ef4f..dcbf2b8 100644
--- a/llvm/test/CodeGen/AMDGPU/mai-hazards.mir
+++ b/llvm/test/CodeGen/AMDGPU/mai-hazards.mir
@@ -25,6 +25,64 @@ body:             |
     $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
 ...
 ---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read
+# GCN:      INLINEASM
+# GCN-NEXT: S_NOP 1
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read
+body:             |
+  bb.0:
+
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr0
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read_partialnop
+# GCN:      INLINEASM
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read_partialnop
+body:             |
+  bb.0:
+
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr0
+    S_NOP 0
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: asm_write_vgpr_accvgpr_write_read_otherreg
+# GCN:      INLINEASM
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            asm_write_vgpr_accvgpr_write_read_otherreg
+body:             |
+  bb.0:
+    liveins: $vgpr0
+    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 1966090 /* regdef:VGPR_32 */, def $vgpr1
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
+# GCN-LABEL: name: bundle_write_vgpr_accvgpr_write_read
+# GCN: BUNDLE
+# GCN-NEXT: S_NOP 0
+# GCN-NEXT: V_MOV_B32
+# GCN-NEXT: }
+# GCN-NEXT: S_NOP 1
+# GCN-NEXT: V_ACCVGPR_WRITE_B32_e64
+name:            bundle_write_vgpr_accvgpr_write_read
+body:             |
+  bb.0:
+    $vgpr0 = BUNDLE {
+      S_NOP 0
+      $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+    }
+    $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
+...
+
+---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_read_same_agpr
 # GCN:      V_MFMA