From: Laurent Pinchart Date: Wed, 1 Jul 2020 13:48:53 +0000 (+0300) Subject: dt-bindings: phy: zynqmp-psgtr: Fix example's numbers of cells in reg X-Git-Tag: v5.15~3208^2~60^2~33 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=574ba3667891b432f92478a02f686bb779a1e593;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: phy: zynqmp-psgtr: Fix example's numbers of cells in reg The DT examples are by default compiled in a parent that has #address-cells and #size-cells both set to 1. Fix the example accordingly, even if it doesn't match the actual hardware, as this is the recommended practice for DT bindings examples. Fixes: cea0f76a483d ("dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY") Signed-off-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200701134853.30656-1-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul --- diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml index 09e3cde7..04d5654 100644 --- a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml +++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml @@ -94,8 +94,8 @@ examples: - | phy: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; - reg = <0x0 0xfd400000 0x0 0x40000>, - <0x0 0xfd3d0000 0x0 0x1000>; + reg = <0xfd400000 0x40000>, + <0xfd3d0000 0x1000>; reg-names = "serdes", "siou"; clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>; clock-names = "ref1", "ref2", "ref3";