From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 11 Jun 2020 08:30:04 +0000 (-0400)
Subject: ac/surface: enable DCC for the first level in the mip tail on gfx10
X-Git-Tag: upstream/21.0.0~8826
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=56f2a77a4149e637d8524780bed121979e7d134e;p=platform%2Fupstream%2Fmesa.git

ac/surface: enable DCC for the first level in the mip tail on gfx10

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
---

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index be55e6d..206cdd2 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1481,7 +1481,16 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
 			 */
 			for (unsigned i = 0; i < in->numMipLevels; i++) {
 				if (meta_mip_info[i].inMiptail) {
-					surf->num_dcc_levels = i;
+					/* GFX10 can only compress the first level
+					 * in the mip tail.
+					 *
+					 * TODO: Try to do the same thing for gfx9
+					 *       if there are no regressions.
+					 */
+					if (info->chip_class >= GFX10)
+						surf->num_dcc_levels = i + 1;
+					else
+						surf->num_dcc_levels = i;
 					break;
 				}
 			}