From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Fri, 27 Sep 2019 20:08:36 +0000 (-0700)
Subject: Merge tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Tag: v5.4-rc1~24
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=568d850e3c6015acec8f854f5be97766497a676b;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'riscv/for-v5.4-rc1-b' of git://git./linux/kernel/git/riscv/linux

Pull more RISC-V updates from Paul Walmsley:
 "Some additional RISC-V updates.

  This includes one significant fix:

   - Prevent interrupts from being unconditionally re-enabled during
     exception handling if they were disabled in the context in which
     the exception occurred

  Also a few other fixes:

   - Fix a build error when sparse memory support is manually enabled

   - Prevent CPUs beyond CONFIG_NR_CPUS from being enabled in early boot

  And a few minor improvements:

   - DT improvements: in the FU540 SoC DT files, improve U-Boot
     compatibility by adding an "ethernet0" alias, drop an unnecessary
     property from the DT files, and add support for the PWM device

   - KVM preparation: add a KVM-related macro for future RISC-V KVM
     support, and export some symbols required to build KVM support as
     modules

   - defconfig additions: build more drivers by default for QEMU
     configurations"

* tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Avoid interrupts being erroneously enabled in handle_exception()
  riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes
  riscv: dts: sifive: Add ethernet0 to the aliases node
  RISC-V: Export kernel symbols for kvm
  KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface
  arch/riscv: disable excess harts before picking main boot hart
  RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig
  RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=y
  riscv: dts: Add DT support for SiFive FU540 PWM driver
---

568d850e3c6015acec8f854f5be97766497a676b
diff --cc arch/riscv/include/asm/pgtable.h
index c60123f,4f4162d..7255f2d
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@@ -424,18 -436,11 +436,6 @@@ extern void *dtb_early_va
  extern void setup_bootmem(void);
  extern void paging_init(void);
  
- #define VMALLOC_SIZE     (KERN_VIRT_SIZE >> 1)
- #define VMALLOC_END      (PAGE_OFFSET - 1)
- #define VMALLOC_START    (PAGE_OFFSET - VMALLOC_SIZE)
- 
- #define FIXADDR_TOP      VMALLOC_START
- #ifdef CONFIG_64BIT
- #define FIXADDR_SIZE     PMD_SIZE
- #else
- #define FIXADDR_SIZE     PGDIR_SIZE
- #endif
- #define FIXADDR_START    (FIXADDR_TOP - FIXADDR_SIZE)
 -static inline void pgtable_cache_init(void)
 -{
 -	/* No page table caches to initialize */
 -}
--
  /*
   * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
   * Note that PGDIR_SIZE must evenly divide TASK_SIZE.