From: Catalin Marinas Date: Tue, 8 May 2007 21:53:44 +0000 (+0100) Subject: [ARM] armv7: add dedicated ARMv7 barrier instructions X-Git-Tag: v3.12-rc1~29692^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=56163fcf194fb688fcf3cefa9b90c5ad41f74059;p=kernel%2Fkernel-generic.git [ARM] armv7: add dedicated ARMv7 barrier instructions Starting with ARMv7, there are dedicated instruction for the ISB, DSB and DMB barriers and there is no need to execute them as CP15 operations. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index c57555c..41dd491 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -158,7 +158,11 @@ extern unsigned int user_debug; #define vectors_high() (0) #endif -#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6 +#if __LINUX_ARM_ARCH__ >= 7 +#define isb() __asm__ __volatile__ ("isb" : : : "memory") +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") +#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \