From: Leo Yan Date: Sat, 21 Jan 2017 02:26:31 +0000 (+0800) Subject: clk: hisilicon: fix lock assignment X-Git-Tag: v4.11-rc1~71^2~23 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=55da97e38cab844682abb71400a908b871d0054c;p=platform%2Fkernel%2Flinux-exynos.git clk: hisilicon: fix lock assignment In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Signed-off-by: Leo Yan Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index a47812f..7908bc3 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->bit_idx = bit_idx; sclk->flags = clk_gate_flags; sclk->hw.init = &init; + sclk->lock = lock; clk = clk_register(dev, &sclk->hw); if (IS_ERR(clk))