From: Stephen Boyd <sboyd@kernel.org>
Date: Fri, 12 Jul 2019 18:07:23 +0000 (-0700)
Subject: Merge tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind... 
X-Git-Tag: v5.15~5910^2^5
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=55692cedf3af29039381e3dbf1b598ab21709d1e;p=platform%2Fkernel%2Flinux-starfive.git

Merge tag 'v5.3-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - New clock-ids+exports for two clocks
 - Cleanup for some boilerplate code for clocks we cannot really control
   from the kernel, but want to define separately to match the
   hardware-description (watchdog in secure-grf)
 - Improvement in mmc phase calculation and cleanup of some rate defintions

* tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: export HDMIPHY clock on rk3228
  clk: rockchip: add watchdog pclk on rk3328
  clk: rockchip: add clock id for hdmi_phy special clock on rk3228
  clk: rockchip: add clock id for watchdog pclk on rk3328
  clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
  clk: rockchip: add a type from SGRF-controlled gate clocks
  clk: rockchip: Remove 48 MHz PLL rate from rk3288
  clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
  clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
  clk: rockchip: Don't yell about bad mmc phases when getting
  clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
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55692cedf3af29039381e3dbf1b598ab21709d1e