From: dramforever Date: Thu, 9 Jun 2022 07:07:29 +0000 (+0800) Subject: include: sbi: Add mtinst/htinst psuedoinstructions X-Git-Tag: v1.3~295 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=551c70c0405b98ae75698d1674c9e0e09fdc6e01;p=platform%2Fkernel%2Fopensbi-spacemit.git include: sbi: Add mtinst/htinst psuedoinstructions Add psuedoinstruction encodings written to mtinst/htinst for faults caused by implicit memory access for VS-stage address translation Signed-off-by: dramforever Reviewed-by: Anup Patel --- diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index a164768..2292858 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -841,6 +841,26 @@ #define INSN_MASK_FENCE_TSO 0xffffffff #define INSN_MATCH_FENCE_TSO 0x8330000f +#if __riscv_xlen == 64 + +/* 64-bit read for VS-stage address translation (RV64) */ +#define INSN_PSEUDO_VS_LOAD 0x00003000 + +/* 64-bit write for VS-stage address translation (RV64) */ +#define INSN_PSEUDO_VS_STORE 0x00003020 + +#elif __riscv_xlen == 32 + +/* 32-bit read for VS-stage address translation (RV32) */ +#define INSN_PSEUDO_VS_LOAD 0x00002000 + +/* 32-bit write for VS-stage address translation (RV32) */ +#define INSN_PSEUDO_VS_STORE 0x00002020 + +#else +#error "Unexpected __riscv_xlen" +#endif + #define INSN_16BIT_MASK 0x3 #define INSN_32BIT_MASK 0x1c